2011-10-05 15:11:40 +00:00
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/*
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* Copyright 2011, Marvell Semiconductor Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-10-05 15:11:40 +00:00
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*
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* Back ported to the 8xx platform (from the 8260 platform) by
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* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
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*/
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#include <common.h>
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#include <command.h>
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#include <config.h>
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#include <net.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <linux/types.h>
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#include <usb/mv_udc.h>
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2013-07-10 01:16:27 +00:00
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#if CONFIG_USB_MAX_CONTROLLER_COUNT > 1
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#error This driver only supports one single controller.
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#endif
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2013-07-10 01:16:38 +00:00
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/*
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* Check if the system has too long cachelines. If the cachelines are
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* longer then 128b, the driver will not be able flush/invalidate data
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* cache over separate QH entries. We use 128b because one QH entry is
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* 64b long and there are always two QH list entries for each endpoint.
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*/
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#if ARCH_DMA_MINALIGN > 128
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#error This driver can not work on systems with caches longer than 128b
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#endif
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2011-10-05 15:11:40 +00:00
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#ifndef DEBUG
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#define DBG(x...) do {} while (0)
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#else
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#define DBG(x...) printf(x)
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static const char *reqname(unsigned r)
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{
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switch (r) {
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case USB_REQ_GET_STATUS: return "GET_STATUS";
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case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
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case USB_REQ_SET_FEATURE: return "SET_FEATURE";
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case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
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case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
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case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
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case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
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case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
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case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
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case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
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default: return "*UNKNOWN*";
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}
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}
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#endif
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static struct usb_endpoint_descriptor ep0_out_desc = {
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.bLength = sizeof(struct usb_endpoint_descriptor),
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.bDescriptorType = USB_DT_ENDPOINT,
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.bEndpointAddress = 0,
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.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
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};
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static struct usb_endpoint_descriptor ep0_in_desc = {
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.bLength = sizeof(struct usb_endpoint_descriptor),
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.bDescriptorType = USB_DT_ENDPOINT,
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.bEndpointAddress = USB_DIR_IN,
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.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
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};
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static int mv_pullup(struct usb_gadget *gadget, int is_on);
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static int mv_ep_enable(struct usb_ep *ep,
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const struct usb_endpoint_descriptor *desc);
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static int mv_ep_disable(struct usb_ep *ep);
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static int mv_ep_queue(struct usb_ep *ep,
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struct usb_request *req, gfp_t gfp_flags);
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static struct usb_request *
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mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
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static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
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static struct usb_gadget_ops mv_udc_ops = {
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.pullup = mv_pullup,
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};
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static struct usb_ep_ops mv_ep_ops = {
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.enable = mv_ep_enable,
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.disable = mv_ep_disable,
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.queue = mv_ep_queue,
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.alloc_request = mv_ep_alloc_request,
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.free_request = mv_ep_free_request,
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};
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2013-07-10 01:16:30 +00:00
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/* Init values for USB endpoints. */
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static const struct usb_ep mv_ep_init[2] = {
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[0] = { /* EP 0 */
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.maxpacket = 64,
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.name = "ep0",
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.ops = &mv_ep_ops,
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},
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[1] = { /* EP 1..n */
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.maxpacket = 512,
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.name = "ep-",
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.ops = &mv_ep_ops,
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},
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};
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2011-10-05 15:11:40 +00:00
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static struct mv_drv controller = {
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2013-07-10 01:16:35 +00:00
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.gadget = {
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.name = "mv_udc",
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.ops = &mv_udc_ops,
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2011-10-05 15:11:40 +00:00
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},
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};
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2013-07-10 01:16:39 +00:00
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/**
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* mv_get_qh() - return queue head for endpoint
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* @ep_num: Endpoint number
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* @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
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*
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* This function returns the QH associated with particular endpoint
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* and it's direction.
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*/
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static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in)
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{
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return &controller.epts[(ep_num * 2) + dir_in];
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}
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2013-07-10 01:16:41 +00:00
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/**
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* mv_get_qtd() - return queue item for endpoint
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* @ep_num: Endpoint number
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* @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
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*
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* This function returns the QH associated with particular endpoint
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* and it's direction.
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*/
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static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in)
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{
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return controller.items[(ep_num * 2) + dir_in];
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}
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2013-07-10 01:16:42 +00:00
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/**
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* mv_flush_qh - flush cache over queue head
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* @ep_num: Endpoint number
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*
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* This function flushes cache over QH for particular endpoint.
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*/
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static void mv_flush_qh(int ep_num)
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{
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struct ept_queue_head *head = mv_get_qh(ep_num, 0);
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const uint32_t start = (uint32_t)head;
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const uint32_t end = start + 2 * sizeof(*head);
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flush_dcache_range(start, end);
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}
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/**
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* mv_invalidate_qh - invalidate cache over queue head
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* @ep_num: Endpoint number
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*
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* This function invalidates cache over QH for particular endpoint.
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*/
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static void mv_invalidate_qh(int ep_num)
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{
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struct ept_queue_head *head = mv_get_qh(ep_num, 0);
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uint32_t start = (uint32_t)head;
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uint32_t end = start + 2 * sizeof(*head);
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invalidate_dcache_range(start, end);
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}
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/**
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* mv_flush_qtd - flush cache over queue item
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* @ep_num: Endpoint number
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*
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* This function flushes cache over qTD pair for particular endpoint.
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*/
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static void mv_flush_qtd(int ep_num)
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{
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struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
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const uint32_t start = (uint32_t)item;
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const uint32_t end_raw = start + 2 * sizeof(*item);
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const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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}
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/**
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* mv_invalidate_qtd - invalidate cache over queue item
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* @ep_num: Endpoint number
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*
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* This function invalidates cache over qTD pair for particular endpoint.
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*/
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static void mv_invalidate_qtd(int ep_num)
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{
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struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
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const uint32_t start = (uint32_t)item;
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const uint32_t end_raw = start + 2 * sizeof(*item);
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const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(start, end);
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}
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2011-10-05 15:11:40 +00:00
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static struct usb_request *
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mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
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{
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struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
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return &mv_ep->req;
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}
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static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
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{
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return;
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}
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static void ep_enable(int num, int in)
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{
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struct ept_queue_head *head;
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2013-07-10 01:16:32 +00:00
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struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
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2011-10-05 15:11:40 +00:00
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unsigned n;
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2013-07-10 01:16:39 +00:00
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head = mv_get_qh(num, in);
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2011-10-05 15:11:40 +00:00
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n = readl(&udc->epctrl[num]);
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if (in)
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n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
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else
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n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
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2013-07-10 01:16:42 +00:00
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if (num != 0) {
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2011-10-05 15:11:40 +00:00
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head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT;
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2013-07-10 01:16:42 +00:00
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mv_flush_qh(num);
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}
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2011-10-05 15:11:40 +00:00
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writel(n, &udc->epctrl[num]);
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}
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static int mv_ep_enable(struct usb_ep *ep,
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const struct usb_endpoint_descriptor *desc)
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{
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struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
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int num, in;
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num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
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ep_enable(num, in);
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mv_ep->desc = desc;
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return 0;
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}
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static int mv_ep_disable(struct usb_ep *ep)
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{
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return 0;
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}
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static int mv_ep_queue(struct usb_ep *ep,
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struct usb_request *req, gfp_t gfp_flags)
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{
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struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
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2013-07-10 01:16:32 +00:00
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struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
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2011-10-05 15:11:40 +00:00
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struct ept_queue_item *item;
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struct ept_queue_head *head;
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unsigned phys;
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int bit, num, len, in;
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num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
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2013-07-10 01:16:41 +00:00
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item = mv_get_qtd(num, in);
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2013-07-10 01:16:39 +00:00
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head = mv_get_qh(num, in);
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2011-10-05 15:11:40 +00:00
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phys = (unsigned)req->buf;
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len = req->length;
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item->next = TERMINATE;
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item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
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item->page0 = phys;
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item->page1 = (phys & 0xfffff000) + 0x1000;
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head->next = (unsigned) item;
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head->info = 0;
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DBG("ept%d %s queue len %x, buffer %x\n",
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num, in ? "in" : "out", len, phys);
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if (in)
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bit = EPT_TX(num);
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else
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bit = EPT_RX(num);
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2013-07-10 01:16:42 +00:00
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mv_flush_qh(num);
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mv_flush_qtd(num);
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2011-10-05 15:11:40 +00:00
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writel(bit, &udc->epprime);
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return 0;
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}
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static void handle_ep_complete(struct mv_ep *ep)
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{
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struct ept_queue_item *item;
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int num, in, len;
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num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
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if (num == 0)
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ep->desc = &ep0_out_desc;
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2013-07-10 01:16:41 +00:00
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item = mv_get_qtd(num, in);
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2013-07-10 01:16:42 +00:00
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mv_invalidate_qtd(num);
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2011-10-05 15:11:40 +00:00
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if (item->info & 0xff)
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printf("EP%d/%s FAIL nfo=%x pg0=%x\n",
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num, in ? "in" : "out", item->info, item->page0);
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len = (item->info >> 16) & 0x7fff;
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ep->req.length -= len;
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DBG("ept%d %s complete %x\n",
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num, in ? "in" : "out", len);
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ep->req.complete(&ep->ep, &ep->req);
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if (num == 0) {
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ep->req.length = 0;
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usb_ep_queue(&ep->ep, &ep->req, 0);
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ep->desc = &ep0_in_desc;
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}
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}
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#define SETUP(type, request) (((type) << 8) | (request))
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static void handle_setup(void)
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{
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2013-07-10 01:16:29 +00:00
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struct usb_request *req = &controller.ep[0].req;
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2013-07-10 01:16:32 +00:00
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struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
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2011-10-05 15:11:40 +00:00
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struct ept_queue_head *head;
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struct usb_ctrlrequest r;
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int status = 0;
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int num, in, _num, _in, i;
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char *buf;
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2013-07-10 01:16:39 +00:00
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head = mv_get_qh(0, 0); /* EP0 OUT */
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2011-10-05 15:11:40 +00:00
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2013-07-10 01:16:42 +00:00
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mv_invalidate_qh(0);
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2011-10-05 15:11:40 +00:00
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memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
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writel(EPT_RX(0), &udc->epstat);
|
|
|
|
DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
|
|
|
|
r.bRequestType, r.bRequest, r.wIndex, r.wValue);
|
|
|
|
|
|
|
|
switch (SETUP(r.bRequestType, r.bRequest)) {
|
|
|
|
case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
|
|
|
|
_num = r.wIndex & 15;
|
|
|
|
_in = !!(r.wIndex & 0x80);
|
|
|
|
|
|
|
|
if ((r.wValue == 0) && (r.wLength == 0)) {
|
|
|
|
req->length = 0;
|
|
|
|
for (i = 0; i < NUM_ENDPOINTS; i++) {
|
2013-07-10 01:16:29 +00:00
|
|
|
if (!controller.ep[i].desc)
|
2011-10-05 15:11:40 +00:00
|
|
|
continue;
|
2013-07-10 01:16:29 +00:00
|
|
|
num = controller.ep[i].desc->bEndpointAddress
|
|
|
|
& USB_ENDPOINT_NUMBER_MASK;
|
|
|
|
in = (controller.ep[i].desc->bEndpointAddress
|
2011-10-05 15:11:40 +00:00
|
|
|
& USB_DIR_IN) != 0;
|
|
|
|
if ((num == _num) && (in == _in)) {
|
|
|
|
ep_enable(num, in);
|
|
|
|
usb_ep_queue(controller.gadget.ep0,
|
|
|
|
req, 0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
|
|
|
|
case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
|
|
|
|
/*
|
|
|
|
* write address delayed (will take effect
|
|
|
|
* after the next IN txn)
|
|
|
|
*/
|
|
|
|
writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
|
|
|
|
req->length = 0;
|
|
|
|
usb_ep_queue(controller.gadget.ep0, req, 0);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
|
|
|
|
req->length = 2;
|
|
|
|
buf = (char *)req->buf;
|
|
|
|
buf[0] = 1 << USB_DEVICE_SELF_POWERED;
|
|
|
|
buf[1] = 0;
|
|
|
|
usb_ep_queue(controller.gadget.ep0, req, 0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* pass request up to the gadget driver */
|
|
|
|
if (controller.driver)
|
|
|
|
status = controller.driver->setup(&controller.gadget, &r);
|
|
|
|
else
|
|
|
|
status = -ENODEV;
|
|
|
|
|
|
|
|
if (!status)
|
|
|
|
return;
|
|
|
|
DBG("STALL reqname %s type %x value %x, index %x\n",
|
|
|
|
reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
|
|
|
|
writel((1<<16) | (1 << 0), &udc->epctrl[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stop_activity(void)
|
|
|
|
{
|
|
|
|
int i, num, in;
|
|
|
|
struct ept_queue_head *head;
|
2013-07-10 01:16:32 +00:00
|
|
|
struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
|
2011-10-05 15:11:40 +00:00
|
|
|
writel(readl(&udc->epcomp), &udc->epcomp);
|
|
|
|
writel(readl(&udc->epstat), &udc->epstat);
|
|
|
|
writel(0xffffffff, &udc->epflush);
|
|
|
|
|
|
|
|
/* error out any pending reqs */
|
|
|
|
for (i = 0; i < NUM_ENDPOINTS; i++) {
|
|
|
|
if (i != 0)
|
|
|
|
writel(0, &udc->epctrl[i]);
|
2013-07-10 01:16:29 +00:00
|
|
|
if (controller.ep[i].desc) {
|
|
|
|
num = controller.ep[i].desc->bEndpointAddress
|
2011-10-05 15:11:40 +00:00
|
|
|
& USB_ENDPOINT_NUMBER_MASK;
|
2013-07-10 01:16:29 +00:00
|
|
|
in = (controller.ep[i].desc->bEndpointAddress
|
|
|
|
& USB_DIR_IN) != 0;
|
2013-07-10 01:16:39 +00:00
|
|
|
head = mv_get_qh(num, in);
|
2011-10-05 15:11:40 +00:00
|
|
|
head->info = INFO_ACTIVE;
|
2013-07-10 01:16:42 +00:00
|
|
|
mv_flush_qh(num);
|
2011-10-05 15:11:40 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void udc_irq(void)
|
|
|
|
{
|
2013-07-10 01:16:32 +00:00
|
|
|
struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
|
2011-10-05 15:11:40 +00:00
|
|
|
unsigned n = readl(&udc->usbsts);
|
|
|
|
writel(n, &udc->usbsts);
|
|
|
|
int bit, i, num, in;
|
|
|
|
|
|
|
|
n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
|
|
|
|
if (n == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (n & STS_URI) {
|
|
|
|
DBG("-- reset --\n");
|
|
|
|
stop_activity();
|
|
|
|
}
|
|
|
|
if (n & STS_SLI)
|
|
|
|
DBG("-- suspend --\n");
|
|
|
|
|
|
|
|
if (n & STS_PCI) {
|
|
|
|
DBG("-- portchange --\n");
|
|
|
|
bit = (readl(&udc->portsc) >> 26) & 3;
|
|
|
|
if (bit == 2) {
|
|
|
|
controller.gadget.speed = USB_SPEED_HIGH;
|
|
|
|
for (i = 1; i < NUM_ENDPOINTS && n; i++)
|
2013-07-10 01:16:29 +00:00
|
|
|
if (controller.ep[i].desc)
|
|
|
|
controller.ep[i].ep.maxpacket = 512;
|
2011-10-05 15:11:40 +00:00
|
|
|
} else {
|
|
|
|
controller.gadget.speed = USB_SPEED_FULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (n & STS_UEI)
|
|
|
|
printf("<UEI %x>\n", readl(&udc->epcomp));
|
|
|
|
|
|
|
|
if ((n & STS_UI) || (n & STS_UEI)) {
|
|
|
|
n = readl(&udc->epstat);
|
|
|
|
if (n & EPT_RX(0))
|
|
|
|
handle_setup();
|
|
|
|
|
|
|
|
n = readl(&udc->epcomp);
|
|
|
|
if (n != 0)
|
|
|
|
writel(n, &udc->epcomp);
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_ENDPOINTS && n; i++) {
|
2013-07-10 01:16:29 +00:00
|
|
|
if (controller.ep[i].desc) {
|
|
|
|
num = controller.ep[i].desc->bEndpointAddress
|
2011-10-05 15:11:40 +00:00
|
|
|
& USB_ENDPOINT_NUMBER_MASK;
|
2013-07-10 01:16:29 +00:00
|
|
|
in = (controller.ep[i].desc->bEndpointAddress
|
2011-10-05 15:11:40 +00:00
|
|
|
& USB_DIR_IN) != 0;
|
|
|
|
bit = (in) ? EPT_TX(num) : EPT_RX(num);
|
|
|
|
if (n & bit)
|
2013-07-10 01:16:29 +00:00
|
|
|
handle_ep_complete(&controller.ep[i]);
|
2011-10-05 15:11:40 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int usb_gadget_handle_interrupts(void)
|
|
|
|
{
|
|
|
|
u32 value;
|
2013-07-10 01:16:32 +00:00
|
|
|
struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
|
2011-10-05 15:11:40 +00:00
|
|
|
|
|
|
|
value = readl(&udc->usbsts);
|
|
|
|
if (value)
|
|
|
|
udc_irq();
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mv_pullup(struct usb_gadget *gadget, int is_on)
|
|
|
|
{
|
2013-07-10 01:16:32 +00:00
|
|
|
struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
|
2011-10-05 15:11:40 +00:00
|
|
|
if (is_on) {
|
|
|
|
/* RESET */
|
|
|
|
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
|
|
|
|
udelay(200);
|
|
|
|
|
2013-07-10 01:16:39 +00:00
|
|
|
writel((unsigned)controller.epts, &udc->epinitaddr);
|
2011-10-05 15:11:40 +00:00
|
|
|
|
|
|
|
/* select DEVICE mode */
|
|
|
|
writel(USBMODE_DEVICE, &udc->usbmode);
|
|
|
|
|
|
|
|
writel(0xffffffff, &udc->epflush);
|
|
|
|
|
|
|
|
/* Turn on the USB connection by enabling the pullup resistor */
|
|
|
|
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
|
|
|
|
} else {
|
|
|
|
stop_activity();
|
|
|
|
writel(USBCMD_FS2, &udc->usbcmd);
|
|
|
|
udelay(800);
|
|
|
|
if (controller.driver)
|
|
|
|
controller.driver->disconnect(gadget);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void udc_disconnect(void)
|
|
|
|
{
|
2013-07-10 01:16:32 +00:00
|
|
|
struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
|
2011-10-05 15:11:40 +00:00
|
|
|
/* disable pullup */
|
|
|
|
stop_activity();
|
|
|
|
writel(USBCMD_FS2, &udc->usbcmd);
|
|
|
|
udelay(800);
|
|
|
|
if (controller.driver)
|
|
|
|
controller.driver->disconnect(&controller.gadget);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mvudc_probe(void)
|
|
|
|
{
|
|
|
|
struct ept_queue_head *head;
|
2013-07-10 01:16:40 +00:00
|
|
|
uint8_t *imem;
|
2011-10-05 15:11:40 +00:00
|
|
|
int i;
|
2013-07-10 01:16:37 +00:00
|
|
|
|
2013-07-10 01:16:34 +00:00
|
|
|
const int num = 2 * NUM_ENDPOINTS;
|
2011-10-05 15:11:40 +00:00
|
|
|
|
2013-07-10 01:16:37 +00:00
|
|
|
const int eplist_min_align = 4096;
|
|
|
|
const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
|
|
|
|
const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
|
|
|
|
const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
|
|
|
|
|
2013-07-10 01:16:40 +00:00
|
|
|
const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
|
|
|
|
const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
|
|
|
|
const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
|
|
|
|
const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
|
|
|
|
|
2013-07-10 01:16:37 +00:00
|
|
|
/* The QH list must be aligned to 4096 bytes. */
|
|
|
|
controller.epts = memalign(eplist_align, eplist_sz);
|
|
|
|
if (!controller.epts)
|
|
|
|
return -ENOMEM;
|
|
|
|
memset(controller.epts, 0, eplist_sz);
|
|
|
|
|
2013-07-10 01:16:40 +00:00
|
|
|
/*
|
|
|
|
* Each qTD item must be 32-byte aligned, each qTD touple must be
|
|
|
|
* cacheline aligned. There are two qTD items for each endpoint and
|
|
|
|
* only one of them is used for the endpoint at time, so we can group
|
|
|
|
* them together.
|
|
|
|
*/
|
|
|
|
controller.items_mem = memalign(ilist_align, ilist_sz);
|
|
|
|
if (!controller.items_mem) {
|
|
|
|
free(controller.epts);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2011-10-05 15:11:40 +00:00
|
|
|
for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
|
|
|
|
/*
|
2013-07-10 01:16:37 +00:00
|
|
|
* Configure QH for each endpoint. The structure of the QH list
|
|
|
|
* is such that each two subsequent fields, N and N+1 where N is
|
|
|
|
* even, in the QH list represent QH for one endpoint. The Nth
|
|
|
|
* entry represents OUT configuration and the N+1th entry does
|
|
|
|
* represent IN configuration of the endpoint.
|
2011-10-05 15:11:40 +00:00
|
|
|
*/
|
2013-07-10 01:16:36 +00:00
|
|
|
head = controller.epts + i;
|
2011-10-05 15:11:40 +00:00
|
|
|
if (i < 2)
|
|
|
|
head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
|
|
|
|
| CONFIG_ZLT | CONFIG_IOS;
|
|
|
|
else
|
|
|
|
head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
|
|
|
|
| CONFIG_ZLT;
|
|
|
|
head->next = TERMINATE;
|
|
|
|
head->info = 0;
|
|
|
|
|
2013-07-10 01:16:40 +00:00
|
|
|
imem = controller.items_mem + ((i >> 1) * ilist_ent_sz);
|
|
|
|
if (i & 1)
|
|
|
|
imem += sizeof(struct ept_queue_item);
|
|
|
|
|
|
|
|
controller.items[i] = (struct ept_queue_item *)imem;
|
2013-07-10 01:16:42 +00:00
|
|
|
|
|
|
|
if (i & 1) {
|
|
|
|
mv_flush_qh(i - 1);
|
|
|
|
mv_flush_qtd(i - 1);
|
|
|
|
}
|
2011-10-05 15:11:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&controller.gadget.ep_list);
|
2013-07-10 01:16:30 +00:00
|
|
|
|
|
|
|
/* Init EP 0 */
|
|
|
|
memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init));
|
2013-07-10 01:16:29 +00:00
|
|
|
controller.ep[0].desc = &ep0_in_desc;
|
2013-07-10 01:16:30 +00:00
|
|
|
controller.gadget.ep0 = &controller.ep[0].ep;
|
2011-10-05 15:11:40 +00:00
|
|
|
INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
|
2013-07-10 01:16:30 +00:00
|
|
|
|
|
|
|
/* Init EP 1..n */
|
|
|
|
for (i = 1; i < NUM_ENDPOINTS; i++) {
|
|
|
|
memcpy(&controller.ep[i].ep, &mv_ep_init[1],
|
|
|
|
sizeof(*mv_ep_init));
|
|
|
|
list_add_tail(&controller.ep[i].ep.ep_list,
|
|
|
|
&controller.gadget.ep_list);
|
2011-10-05 15:11:40 +00:00
|
|
|
}
|
2013-07-10 01:16:30 +00:00
|
|
|
|
2011-10-05 15:11:40 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
|
|
|
|
{
|
2013-07-10 01:16:32 +00:00
|
|
|
struct mv_udc *udc;
|
|
|
|
int ret;
|
2011-10-05 15:11:40 +00:00
|
|
|
|
2013-07-10 01:16:33 +00:00
|
|
|
if (!driver)
|
|
|
|
return -EINVAL;
|
|
|
|
if (!driver->bind || !driver->setup || !driver->disconnect)
|
|
|
|
return -EINVAL;
|
|
|
|
if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
|
2011-10-05 15:11:40 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
2013-07-10 01:16:32 +00:00
|
|
|
ret = usb_lowlevel_init(0, (void **)&controller.ctrl);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = mvudc_probe();
|
|
|
|
if (!ret) {
|
|
|
|
udc = (struct mv_udc *)controller.ctrl->hcor;
|
|
|
|
|
2011-10-05 15:11:40 +00:00
|
|
|
/* select ULPI phy */
|
|
|
|
writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
|
|
|
|
}
|
2013-07-10 01:16:32 +00:00
|
|
|
|
|
|
|
ret = driver->bind(&controller.gadget);
|
|
|
|
if (ret) {
|
|
|
|
DBG("driver->bind() returned %d\n", ret);
|
|
|
|
return ret;
|
2011-10-05 15:11:40 +00:00
|
|
|
}
|
|
|
|
controller.driver = driver;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|