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https://github.com/AsahiLinux/u-boot
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582 lines
17 KiB
C
582 lines
17 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* Interface to the hardware Fetch and Add Unit.
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*/
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#ifndef __CVMX_FAU_H__
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#define __CVMX_FAU_H__
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extern u8 *cvmx_fau_regs_ptr;
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/**
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* Initializes fau, on devices with FAU hw this is a noop.
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*/
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int cvmx_fau_init(void);
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/**
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* Return the location of emulated FAU register
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*/
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static inline u8 *__cvmx_fau_sw_addr(int reg)
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{
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if (cvmx_unlikely(!cvmx_fau_regs_ptr))
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cvmx_fau_init();
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return (cvmx_fau_regs_ptr + reg);
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}
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/**
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* Perform an atomic 64 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg64_t reg,
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int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add64(reg, value);
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return __atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 32 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg32_t reg,
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int32_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add32(reg, value);
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reg ^= SWIZZLE_32;
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return __atomic_fetch_add(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 16 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg16_t reg,
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int16_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add16(reg, value);
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reg ^= SWIZZLE_16;
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return __atomic_fetch_add(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 8 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add8(reg, value);
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reg ^= SWIZZLE_8;
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return __atomic_fetch_add(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 64 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait64_t
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cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg64_t reg, int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add64(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait64_t){ 1, 0 };
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}
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/**
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* Perform an atomic 32 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait32_t
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cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg32_t reg, int32_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add32(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait32_t){ 1, 0 };
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}
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/**
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* Perform an atomic 16 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait16_t
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cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg16_t reg, int16_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add16(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait16_t){ 1, 0 };
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}
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/**
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* Perform an atomic 8 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait8_t
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cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add8(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait8_t){ 1, 0 };
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}
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/**
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* Perform an async atomic 64 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void
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cvmx_fau_async_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_fetch_and_add64(scraddr, reg, value);
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return;
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}
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 32 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void
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cvmx_fau_async_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, int32_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_fetch_and_add32(scraddr, reg, value);
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return;
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}
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 16 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void
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cvmx_fau_async_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, int16_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_fetch_and_add16(scraddr, reg, value);
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return;
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}
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 8 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void
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cvmx_fau_async_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_fetch_and_add8(scraddr, reg, value);
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return;
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}
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 64 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
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* the value of the register before the update will be
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_tagwait_fetch_and_add64(u64 scraddr,
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cvmx_fau_reg64_t reg,
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int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_tagwait_fetch_and_add64(scraddr, reg, value);
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return;
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}
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/* Broken. Where is the tag wait? */
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 32 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
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* the value of the register before the update will be
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_tagwait_fetch_and_add32(u64 scraddr,
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cvmx_fau_reg32_t reg,
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int32_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_tagwait_fetch_and_add32(scraddr, reg, value);
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return;
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}
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/* Broken. Where is the tag wait? */
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 16 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
|
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* the value of the register before the update will be
|
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_tagwait_fetch_and_add16(u64 scraddr,
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cvmx_fau_reg16_t reg,
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int16_t value)
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|
{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_tagwait_fetch_and_add16(scraddr, reg, value);
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return;
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}
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/* Broken. Where is the tag wait? */
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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||
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/**
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* Perform an async atomic 8 bit add after the current tag
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* switch completes.
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||
|
*
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* @param scraddr Scratch memory byte address to put response in.
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||
|
* Must be 8 byte aligned.
|
||
|
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
||
|
* the value of the register before the update will be
|
||
|
* returned
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
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||
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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||
|
*/
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||
|
static inline void cvmx_fau_async_tagwait_fetch_and_add8(u64 scraddr,
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||
|
cvmx_fau_reg8_t reg,
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||
|
int8_t value)
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||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_async_tagwait_fetch_and_add8(scraddr, reg, value);
|
||
|
return;
|
||
|
}
|
||
|
/* Broken. Where is the tag wait? */
|
||
|
cvmx_scratch_write64(
|
||
|
scraddr,
|
||
|
__atomic_fetch_add(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)),
|
||
|
value, __ATOMIC_SEQ_CST));
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 64 bit add
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* - Step by 8 for 64 bit access.
|
||
|
* @param value Signed value to add.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_add64(cvmx_fau_reg64_t reg, int64_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_add64(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
/* Ignored fetch values should be optimized away */
|
||
|
__atomic_add_fetch(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 32 bit add
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* - Step by 4 for 32 bit access.
|
||
|
* @param value Signed value to add.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_add32(cvmx_fau_reg32_t reg, int32_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_add32(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
reg ^= SWIZZLE_32;
|
||
|
/* Ignored fetch values should be optimized away */
|
||
|
__atomic_add_fetch(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 16 bit add
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* - Step by 2 for 16 bit access.
|
||
|
* @param value Signed value to add.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_add16(cvmx_fau_reg16_t reg, int16_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_add16(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
reg ^= SWIZZLE_16;
|
||
|
/* Ignored fetch values should be optimized away */
|
||
|
__atomic_add_fetch(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 8 bit add
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* @param value Signed value to add.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_add8(cvmx_fau_reg8_t reg, int8_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_add8(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
reg ^= SWIZZLE_8;
|
||
|
/* Ignored fetch values should be optimized away */
|
||
|
__atomic_add_fetch(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 64 bit write
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* - Step by 8 for 64 bit access.
|
||
|
* @param value Signed value to write.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_write64(cvmx_fau_reg64_t reg, int64_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_write64(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
__atomic_store_n(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 32 bit write
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* - Step by 4 for 32 bit access.
|
||
|
* @param value Signed value to write.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_write32(cvmx_fau_reg32_t reg, int32_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_write32(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
reg ^= SWIZZLE_32;
|
||
|
__atomic_store_n(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 16 bit write
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* - Step by 2 for 16 bit access.
|
||
|
* @param value Signed value to write.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_write16(cvmx_fau_reg16_t reg, int16_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_write16(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
reg ^= SWIZZLE_16;
|
||
|
__atomic_store_n(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* Perform an atomic 8 bit write
|
||
|
*
|
||
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||
|
* @param value Signed value to write.
|
||
|
*/
|
||
|
static inline void cvmx_fau_atomic_write8(cvmx_fau_reg8_t reg, int8_t value)
|
||
|
{
|
||
|
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||
|
cvmx_hwfau_atomic_write8(reg, value);
|
||
|
return;
|
||
|
}
|
||
|
reg ^= SWIZZLE_8;
|
||
|
__atomic_store_n(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)), value,
|
||
|
__ATOMIC_SEQ_CST);
|
||
|
}
|
||
|
|
||
|
/** Allocates 64bit FAU register.
|
||
|
* @param reserve base address to reserve
|
||
|
* @return value is the base address of allocated FAU register
|
||
|
*/
|
||
|
int cvmx_fau64_alloc(int reserve);
|
||
|
|
||
|
/** Allocates 32bit FAU register.
|
||
|
* @param reserve base address to reserve
|
||
|
* @return value is the base address of allocated FAU register
|
||
|
*/
|
||
|
int cvmx_fau32_alloc(int reserve);
|
||
|
|
||
|
/** Allocates 16bit FAU register.
|
||
|
* @param reserve base address to reserve
|
||
|
* @return value is the base address of allocated FAU register
|
||
|
*/
|
||
|
int cvmx_fau16_alloc(int reserve);
|
||
|
|
||
|
/** Allocates 8bit FAU register.
|
||
|
* @param reserve base address to reserve
|
||
|
* @return value is the base address of allocated FAU register
|
||
|
*/
|
||
|
int cvmx_fau8_alloc(int reserve);
|
||
|
|
||
|
/** Frees the specified FAU register.
|
||
|
* @param address base address of register to release.
|
||
|
* @return 0 on success; -1 on failure
|
||
|
*/
|
||
|
int cvmx_fau_free(int address);
|
||
|
|
||
|
/** Display the fau registers array
|
||
|
*/
|
||
|
void cvmx_fau_show(void);
|
||
|
|
||
|
#endif /* __CVMX_FAU_H__ */
|