2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2016-11-04 10:57:02 +00:00
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/*
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* Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
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* Patrick Bruenn <p.bruenn@beckhoff.com>
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*
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* Configuration settings for Beckhoff CX9020.
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*
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* Based on Freescale's Linux i.MX mx53loco.h file:
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* Copyright (C) 2010-2011 Freescale Semiconductor.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_REVISION_TAG
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#define CONFIG_MXC_UART_BASE UART2_BASE
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#define CONFIG_FPGA_COUNT 1
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 2
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/* bootz: zImage/initrd.img support */
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/* Eth Configs */
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_ETHPRIME "FEC0"
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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/* USB Configs */
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#define CONFIG_MXC_USB_PORT 1
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command definition */
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#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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2017-07-11 09:23:20 +00:00
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"fdt_addr_r=0x71ff0000\0" \
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2017-07-11 09:23:21 +00:00
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"pxefile_addr_r=0x73000000\0" \
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2017-07-11 09:23:20 +00:00
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"ramdisk_addr_r=0x72000000\0" \
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2016-11-04 10:57:02 +00:00
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"console=ttymxc1,115200\0" \
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"uenv=/boot/uEnv.txt\0" \
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"optargs=\0" \
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"cmdline=\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcrootfstype=ext4 rootwait fixrtc\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
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"rootfstype=${mmcrootfstype} " \
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"${cmdline}\0" \
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"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
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2017-07-11 09:23:21 +00:00
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"loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \
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2017-07-11 09:23:20 +00:00
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"loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \
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2016-11-04 10:57:02 +00:00
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"setenv rdsize ${filesize}\0" \
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"loadfdt=echo loading ${fdt_path} ...;" \
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2017-07-11 09:23:20 +00:00
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"load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \
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2016-11-04 10:57:02 +00:00
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"mmcboot=mmc dev ${mmcdev}; " \
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"if mmc rescan; then " \
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"echo SD/MMC found on device ${mmcdev};" \
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"echo Checking for: ${uenv} ...;" \
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"setenv bootpart ${mmcdev}:${mmcpart};" \
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"if test -e mmc ${bootpart} ${uenv}; then " \
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"load mmc ${bootpart} ${loadaddr} ${uenv};" \
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"env import -t ${loadaddr} ${filesize};" \
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"echo Loaded environment from ${uenv};" \
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"if test -n ${dtb}; then " \
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"setenv fdt_file ${dtb};" \
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"echo Using: dtb=${fdt_file} ...;" \
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"fi;" \
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"echo Checking for uname_r in ${uenv}...;" \
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"if test -n ${uname_r}; then " \
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"echo Running uname_boot ...;" \
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"run uname_boot;" \
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"fi;" \
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"fi;" \
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"fi;\0" \
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"uname_boot="\
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"setenv bootdir /boot; " \
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"setenv bootfile vmlinuz-${uname_r}; " \
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"setenv ccatfile /boot/ccat.rbf; " \
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"echo loading CCAT firmware from ${ccatfile}; " \
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"load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
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"fpga load 0 ${loadaddr} ${filesize}; " \
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"if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
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"echo loading ${bootdir}/${bootfile} ...; " \
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"run loadimage;" \
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"setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
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"if test -e mmc ${bootpart} ${fdt_path}; then " \
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"run loadfdt;" \
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"else " \
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"echo; echo unable to find ${fdt_file} ...;" \
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"echo booting legacy ...;"\
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"run mmcargs;" \
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"echo debug: [${bootargs}] ... ;" \
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"echo debug: [bootz ${loadaddr}] ... ;" \
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"bootz ${loadaddr}; " \
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"fi;" \
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"run mmcargs;" \
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"echo debug: [${bootargs}] ... ;" \
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2017-07-11 09:23:20 +00:00
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"echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \
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"bootz ${loadaddr} - ${fdt_addr_r}; " \
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2017-07-11 09:23:21 +00:00
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"else " \
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"echo loading from dhcp ...; " \
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"run loadpxe; " \
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2016-11-04 10:57:02 +00:00
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"run mmcboot;"
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#define CONFIG_ARP_TIMEOUT 200UL
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x70000000
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#define CONFIG_SYS_MEMTEST_END 0x70010000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
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#define PHYS_SDRAM_2 CSD1_BASE_ADDR
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#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
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#define PHYS_SDRAM_SIZE (gd->ram_size)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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2017-02-11 13:43:54 +00:00
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/* environment organization */
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2016-11-04 10:57:02 +00:00
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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/* Framebuffer and LCD */
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2019-04-17 11:57:17 +00:00
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#define CONFIG_IMX_VIDEO_SKIP
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2016-11-04 10:57:02 +00:00
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#endif /* __CONFIG_H */
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