u-boot/arch/arm/mach-tegra/tegra186/Makefile

# Copyright (c) 2016, NVIDIA CORPORATION.
#
# SPDX-License-Identifier: GPL-2.0

obj-y += ../board186.o
obj-y += cache.o
obj-y += nvtboot_ll.o
obj-y += nvtboot_mem.o
ARM: tegra: add core Tegra186 support This adds the bare minimum code to support Tegra186, with UART and eMMC working. The empty gpio.h is required because <asm/gpio.h> includes it. A future cleanup round may be able to solve this for all Tegra generations at once. mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but instead to defer everything to mach-tegra/tegra186/Makefile. This allows the SoC code to pick-and-choose which of the C files in the "common" mach-tegra/ directory to compile in based on the SoC's needs. Most of the code is not valid for Tegra186, and this approach removes the need for mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach may be applied to all other Tegra SoCs in a future cleanup round. board186.c is introduced to replace board.c and board2.c. These files currently contain a slew of SoC- and board-specific code that is not valid for Tegra186. This approach avoids adding yet more ifdefs to those files. A future cleanup round may refactor most of board*.c into board-/ SoC-specific functions files thus allowing the top-level functions like board_init_early_f to be shared again. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 2016-05-12 19:32:55 +00:00			`# Copyright (c) 2016, NVIDIA CORPORATION.`
			`#`
			`# SPDX-License-Identifier: GPL-2.0`

			`obj-y += ../board186.o`
ARM: tegra: flush caches via SMC call On Tegra186, it is necessary to perform an SMC to fully flush all caches; flushing/cleaning by set/way is not enough. Implement the required hook to make this happen. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 2016-09-23 23:43:49 +00:00			`obj-y += cache.o`
ARM: tegra: pick up actual memory size On Tegra186, U-Boot is booted by the binary firmware as if it were a Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address of that DTB, and parse the /memory/reg property to determine the actual RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use. Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion that U-Boot use that DTB as its control DTB. I don't believe that would work well, so I do not plan to put any effort into this. By default the FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT bindings. U-Boot aims to use only upstreamed DT bindings, or as close as it can get. Replacing this DTB with a DTB using upstream bindings is physically quite easy; simply replace the content of one of the GPT partitions on the eMMC. However, the binary FW at least partially relies on the existence/content of some nodes in the DTB, and that requires the DTB to be written according to downstream bindings. Equally, if U-Boot continues to use appended DTBs built from its own source tree, as it does for all other Tegra platforms, development and deployment is much easier. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 2016-07-18 23:01:51 +00:00			`obj-y += nvtboot_ll.o`
			`obj-y += nvtboot_mem.o`