2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-11-25 00:18:01 +00:00
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/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*/
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2014-10-08 20:57:52 +00:00
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#include <bootm.h>
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2011-11-25 00:18:01 +00:00
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#include <common.h>
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2014-10-08 20:57:52 +00:00
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#include <netdev.h>
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2016-09-21 02:28:55 +00:00
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#include <linux/errno.h>
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2011-11-25 00:18:01 +00:00
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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2012-04-29 08:11:13 +00:00
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#include <asm/arch/crm_regs.h>
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2018-01-10 05:20:34 +00:00
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#include <asm/mach-imx/boot_mode.h>
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2015-05-18 13:56:46 +00:00
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#include <imx_thermal.h>
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2012-09-23 07:30:55 +00:00
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#include <ipu_pixfmt.h>
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2014-11-20 13:14:14 +00:00
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#include <thermal.h>
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2014-11-21 10:47:26 +00:00
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#include <sata.h>
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2011-11-25 00:18:01 +00:00
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2019-06-21 03:42:28 +00:00
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#ifdef CONFIG_FSL_ESDHC_IMX
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#include <fsl_esdhc_imx.h>
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2011-11-25 00:18:01 +00:00
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#endif
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2015-02-15 21:37:21 +00:00
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static u32 reset_cause = -1;
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2019-02-01 15:04:51 +00:00
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u32 get_imx_reset_cause(void)
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2011-11-25 00:18:01 +00:00
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{
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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2019-02-01 15:04:51 +00:00
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if (reset_cause == -1) {
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reset_cause = readl(&src_regs->srsr);
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/* preserve the value for U-Boot proper */
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#if !defined(CONFIG_SPL_BUILD)
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writel(reset_cause, &src_regs->srsr);
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#endif
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}
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return reset_cause;
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}
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2011-11-25 00:18:01 +00:00
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2019-02-01 15:04:51 +00:00
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#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
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static char *get_reset_cause(void)
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{
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switch (get_imx_reset_cause()) {
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2011-11-25 00:18:01 +00:00
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case 0x00001:
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2012-03-13 07:26:48 +00:00
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case 0x00011:
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2011-11-25 00:18:01 +00:00
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return "POR";
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case 0x00004:
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return "CSU";
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case 0x00008:
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return "IPP USER";
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case 0x00010:
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2015-09-02 18:54:23 +00:00
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#ifdef CONFIG_MX7
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return "WDOG1";
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#else
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2011-11-25 00:18:01 +00:00
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return "WDOG";
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2015-09-02 18:54:23 +00:00
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#endif
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2011-11-25 00:18:01 +00:00
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case 0x00020:
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return "JTAG HIGH-Z";
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case 0x00040:
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return "JTAG SW";
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2015-09-02 18:54:23 +00:00
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case 0x00080:
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return "WDOG3";
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#ifdef CONFIG_MX7
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case 0x00100:
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return "WDOG4";
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case 0x00200:
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return "TEMPSENSE";
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2018-11-20 10:19:25 +00:00
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#elif defined(CONFIG_IMX8M)
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2018-01-10 05:20:25 +00:00
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case 0x00100:
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return "WDOG2";
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case 0x00200:
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return "TEMPSENSE";
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2015-09-02 18:54:23 +00:00
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#else
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case 0x00100:
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return "TEMPSENSE";
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2011-11-25 00:18:01 +00:00
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case 0x10000:
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return "WARM BOOT";
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2015-09-02 18:54:23 +00:00
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#endif
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2011-11-25 00:18:01 +00:00
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default:
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return "unknown reset";
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}
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}
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2015-05-18 11:43:52 +00:00
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#endif
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2015-02-15 21:37:21 +00:00
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2017-08-28 19:46:26 +00:00
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#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
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2012-03-20 04:21:45 +00:00
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2012-10-23 10:57:46 +00:00
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const char *get_imx_type(u32 imxtype)
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2012-03-20 04:21:45 +00:00
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{
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switch (imxtype) {
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2019-12-27 02:14:02 +00:00
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case MXC_CPU_IMX8MP:
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return "8MP"; /* Quad-core version of the imx8mp */
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2019-06-27 09:23:49 +00:00
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case MXC_CPU_IMX8MN:
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2020-02-05 09:39:27 +00:00
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return "8MNano Quad"; /* Quad-core version */
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case MXC_CPU_IMX8MND:
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return "8MNano Dual"; /* Dual-core version */
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case MXC_CPU_IMX8MNS:
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return "8MNano Solo"; /* Single-core version */
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case MXC_CPU_IMX8MNL:
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return "8MNano QuadLite"; /* Quad-core Lite version */
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case MXC_CPU_IMX8MNDL:
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return "8MNano DualLite"; /* Dual-core Lite version */
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case MXC_CPU_IMX8MNSL:
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return "8MNano SoloLite"; /* Single-core Lite version */
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2019-08-27 06:25:04 +00:00
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case MXC_CPU_IMX8MM:
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return "8MMQ"; /* Quad-core version of the imx8mm */
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case MXC_CPU_IMX8MML:
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return "8MMQL"; /* Quad-core Lite version of the imx8mm */
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case MXC_CPU_IMX8MMD:
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return "8MMD"; /* Dual-core version of the imx8mm */
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case MXC_CPU_IMX8MMDL:
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return "8MMDL"; /* Dual-core Lite version of the imx8mm */
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case MXC_CPU_IMX8MMS:
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return "8MMS"; /* Single-core version of the imx8mm */
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case MXC_CPU_IMX8MMSL:
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return "8MMSL"; /* Single-core Lite version of the imx8mm */
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2018-11-20 10:19:25 +00:00
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case MXC_CPU_IMX8MQ:
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2020-02-05 09:34:54 +00:00
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return "8MQ"; /* Quad-core version of the imx8mq */
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case MXC_CPU_IMX8MQL:
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return "8MQLite"; /* Quad-core Lite version of the imx8mq */
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case MXC_CPU_IMX8MD:
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return "8MD"; /* Dual-core version of the imx8mq */
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2016-02-28 15:33:17 +00:00
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case MXC_CPU_MX7S:
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2016-05-06 18:21:50 +00:00
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return "7S"; /* Single-core version of the mx7 */
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2015-09-02 18:54:23 +00:00
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case MXC_CPU_MX7D:
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return "7D"; /* Dual-core version of the mx7 */
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2015-07-11 03:38:42 +00:00
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case MXC_CPU_MX6QP:
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return "6QP"; /* Quad-Plus version of the mx6 */
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case MXC_CPU_MX6DP:
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return "6DP"; /* Dual-Plus version of the mx6 */
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2012-10-23 10:57:46 +00:00
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case MXC_CPU_MX6Q:
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2012-03-20 04:21:45 +00:00
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return "6Q"; /* Quad-core version of the mx6 */
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2014-01-26 17:06:41 +00:00
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case MXC_CPU_MX6D:
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return "6D"; /* Dual-core version of the mx6 */
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2012-10-23 10:57:46 +00:00
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case MXC_CPU_MX6DL:
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return "6DL"; /* Dual Lite version of the mx6 */
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case MXC_CPU_MX6SOLO:
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return "6SOLO"; /* Solo version of the mx6 */
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case MXC_CPU_MX6SL:
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2012-03-20 04:21:45 +00:00
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return "6SL"; /* Solo-Lite version of the mx6 */
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2016-12-11 11:24:20 +00:00
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case MXC_CPU_MX6SLL:
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return "6SLL"; /* SLL version of the mx6 */
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2014-06-24 20:40:58 +00:00
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case MXC_CPU_MX6SX:
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return "6SX"; /* SoloX version of the mx6 */
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2015-07-20 11:28:21 +00:00
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case MXC_CPU_MX6UL:
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return "6UL"; /* Ultra-Lite version of the mx6 */
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2016-08-11 06:02:38 +00:00
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case MXC_CPU_MX6ULL:
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return "6ULL"; /* ULL version of the mx6 */
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2019-08-08 09:55:52 +00:00
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case MXC_CPU_MX6ULZ:
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return "6ULZ"; /* ULZ version of the mx6 */
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2012-10-23 10:57:46 +00:00
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case MXC_CPU_MX51:
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2012-03-20 04:21:45 +00:00
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return "51";
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2012-10-23 10:57:46 +00:00
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case MXC_CPU_MX53:
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2012-03-20 04:21:45 +00:00
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return "53";
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default:
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2012-06-30 05:07:32 +00:00
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return "??";
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2012-03-20 04:21:45 +00:00
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}
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}
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2011-11-25 00:18:01 +00:00
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int print_cpuinfo(void)
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{
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2015-05-26 17:53:41 +00:00
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u32 cpurev;
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__maybe_unused u32 max_freq;
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2011-11-25 00:18:01 +00:00
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2015-09-02 18:54:13 +00:00
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cpurev = get_cpu_rev();
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#if defined(CONFIG_IMX_THERMAL)
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2014-11-20 13:14:14 +00:00
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struct udevice *thermal_dev;
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2015-05-18 13:56:46 +00:00
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int cpu_tmp, minc, maxc, ret;
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2012-03-20 04:21:45 +00:00
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2015-05-18 14:02:25 +00:00
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printf("CPU: Freescale i.MX%s rev%d.%d",
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2019-12-30 09:57:10 +00:00
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get_imx_type((cpurev & 0x1FF000) >> 12),
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2015-05-18 14:02:25 +00:00
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(cpurev & 0x000F0) >> 4,
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(cpurev & 0x0000F) >> 0);
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max_freq = get_cpu_speed_grade_hz();
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if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
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printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
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} else {
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printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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}
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#else
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2012-03-20 04:21:45 +00:00
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printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
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2019-12-30 09:57:10 +00:00
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get_imx_type((cpurev & 0x1FF000) >> 12),
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2011-11-25 00:18:01 +00:00
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(cpurev & 0x000F0) >> 4,
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(cpurev & 0x0000F) >> 0,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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2015-05-18 14:02:25 +00:00
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#endif
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2014-11-20 13:14:14 +00:00
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2015-09-02 18:54:13 +00:00
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#if defined(CONFIG_IMX_THERMAL)
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2015-05-18 13:56:46 +00:00
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puts("CPU: ");
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switch (get_cpu_temp_grade(&minc, &maxc)) {
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case TEMP_AUTOMOTIVE:
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puts("Automotive temperature grade ");
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break;
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case TEMP_INDUSTRIAL:
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puts("Industrial temperature grade ");
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break;
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case TEMP_EXTCOMMERCIAL:
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puts("Extended Commercial temperature grade ");
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break;
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default:
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puts("Commercial temperature grade ");
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break;
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}
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printf("(%dC to %dC)", minc, maxc);
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2014-11-20 13:14:14 +00:00
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ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
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if (!ret) {
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ret = thermal_get_temp(thermal_dev, &cpu_tmp);
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if (!ret)
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2015-05-18 13:56:46 +00:00
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printf(" at %dC\n", cpu_tmp);
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2014-11-20 13:14:14 +00:00
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else
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2015-09-08 17:43:10 +00:00
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debug(" - invalid sensor data\n");
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2014-11-20 13:14:14 +00:00
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} else {
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2015-09-08 17:43:10 +00:00
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debug(" - invalid sensor device\n");
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2014-11-20 13:14:14 +00:00
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}
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#endif
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2011-11-25 00:18:01 +00:00
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printf("Reset cause: %s\n", get_reset_cause());
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_FEC_MXC)
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rc = fecmxc_initialize(bis);
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#endif
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return rc;
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}
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2019-06-21 03:42:28 +00:00
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#ifdef CONFIG_FSL_ESDHC_IMX
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2011-11-25 00:18:01 +00:00
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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2012-08-17 10:42:55 +00:00
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#endif
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2011-11-25 00:18:01 +00:00
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2018-11-20 10:19:25 +00:00
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#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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2012-04-29 08:11:13 +00:00
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u32 get_ahb_clk(void)
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{
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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u32 reg, ahb_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
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ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
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return get_periph_clk() / (ahb_podf + 1);
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}
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2015-09-02 18:54:23 +00:00
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#endif
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2012-09-23 07:30:55 +00:00
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void arch_preboot_os(void)
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{
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2019-06-09 01:50:51 +00:00
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#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
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2017-05-12 19:58:41 +00:00
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imx_pcie_remove();
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#endif
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2017-06-15 03:28:25 +00:00
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#if defined(CONFIG_SATA)
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2019-07-02 13:10:52 +00:00
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if (!is_mx6sdl()) {
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sata_remove(0);
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2014-11-27 09:11:41 +00:00
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#if defined(CONFIG_MX6)
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2019-07-02 13:10:52 +00:00
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disable_sata_clock();
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2014-11-27 09:11:41 +00:00
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#endif
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2019-07-02 13:10:52 +00:00
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}
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2014-11-21 10:47:26 +00:00
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#endif
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#if defined(CONFIG_VIDEO_IPUV3)
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2012-09-23 07:30:55 +00:00
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/* disable video before launching O/S */
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ipuv3_fb_shutdown();
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#endif
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2019-06-03 21:05:59 +00:00
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#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
|
2015-10-29 07:54:51 +00:00
|
|
|
lcdif_power_down();
|
|
|
|
#endif
|
2014-11-21 10:47:26 +00:00
|
|
|
}
|
2014-11-14 13:27:21 +00:00
|
|
|
|
2018-11-20 10:19:25 +00:00
|
|
|
#ifndef CONFIG_IMX8M
|
2014-11-14 13:27:21 +00:00
|
|
|
void set_chipselect_size(int const cs_size)
|
|
|
|
{
|
|
|
|
unsigned int reg;
|
|
|
|
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
reg = readl(&iomuxc_regs->gpr[1]);
|
|
|
|
|
|
|
|
switch (cs_size) {
|
|
|
|
case CS0_128:
|
|
|
|
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
|
|
|
|
reg |= 0x5;
|
|
|
|
break;
|
|
|
|
case CS0_64M_CS1_64M:
|
|
|
|
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
|
|
|
|
reg |= 0x1B;
|
|
|
|
break;
|
|
|
|
case CS0_64M_CS1_32M_CS2_32M:
|
|
|
|
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
|
|
|
|
reg |= 0x4B;
|
|
|
|
break;
|
|
|
|
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
|
|
|
|
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
|
|
|
|
reg |= 0x249;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("Unknown chip select size: %d\n", cs_size);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(reg, &iomuxc_regs->gpr[1]);
|
|
|
|
}
|
2018-01-10 05:20:25 +00:00
|
|
|
#endif
|
2017-11-27 12:25:09 +00:00
|
|
|
|
2018-11-20 10:19:25 +00:00
|
|
|
#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
|
2018-01-10 05:20:29 +00:00
|
|
|
/*
|
|
|
|
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
|
|
|
|
* defines a 2-bit SPEED_GRADING
|
|
|
|
*/
|
|
|
|
#define OCOTP_TESTER3_SPEED_SHIFT 8
|
2018-01-10 05:20:30 +00:00
|
|
|
enum cpu_speed {
|
|
|
|
OCOTP_TESTER3_SPEED_GRADE0,
|
|
|
|
OCOTP_TESTER3_SPEED_GRADE1,
|
|
|
|
OCOTP_TESTER3_SPEED_GRADE2,
|
|
|
|
OCOTP_TESTER3_SPEED_GRADE3,
|
2018-12-12 10:47:58 +00:00
|
|
|
OCOTP_TESTER3_SPEED_GRADE4,
|
2018-01-10 05:20:30 +00:00
|
|
|
};
|
2018-01-10 05:20:29 +00:00
|
|
|
|
|
|
|
u32 get_cpu_speed_grade_hz(void)
|
|
|
|
{
|
|
|
|
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
|
|
|
struct fuse_bank *bank = &ocotp->bank[1];
|
|
|
|
struct fuse_bank1_regs *fuse =
|
|
|
|
(struct fuse_bank1_regs *)bank->fuse_regs;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = readl(&fuse->tester3);
|
|
|
|
val >>= OCOTP_TESTER3_SPEED_SHIFT;
|
2018-12-12 10:47:58 +00:00
|
|
|
|
2020-01-17 08:11:29 +00:00
|
|
|
if (is_imx8mn() || is_imx8mp()) {
|
2018-12-12 10:47:58 +00:00
|
|
|
val &= 0xf;
|
|
|
|
return 2300000000 - val * 100000000;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_imx8mm())
|
|
|
|
val &= 0x7;
|
|
|
|
else
|
|
|
|
val &= 0x3;
|
2018-01-10 05:20:29 +00:00
|
|
|
|
|
|
|
switch(val) {
|
2018-01-10 05:20:30 +00:00
|
|
|
case OCOTP_TESTER3_SPEED_GRADE0:
|
2018-01-10 05:20:29 +00:00
|
|
|
return 800000000;
|
2018-01-10 05:20:30 +00:00
|
|
|
case OCOTP_TESTER3_SPEED_GRADE1:
|
2018-10-17 06:12:37 +00:00
|
|
|
return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
|
2018-01-10 05:20:30 +00:00
|
|
|
case OCOTP_TESTER3_SPEED_GRADE2:
|
2018-10-17 06:12:37 +00:00
|
|
|
return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
|
2018-01-10 05:20:30 +00:00
|
|
|
case OCOTP_TESTER3_SPEED_GRADE3:
|
2018-10-17 06:12:37 +00:00
|
|
|
return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
|
2018-12-12 10:47:58 +00:00
|
|
|
case OCOTP_TESTER3_SPEED_GRADE4:
|
|
|
|
return 2000000000;
|
2018-01-10 05:20:29 +00:00
|
|
|
}
|
2018-01-10 05:20:30 +00:00
|
|
|
|
2018-01-10 05:20:29 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
|
|
|
|
* defines a 2-bit SPEED_GRADING
|
|
|
|
*/
|
|
|
|
#define OCOTP_TESTER3_TEMP_SHIFT 6
|
|
|
|
|
|
|
|
u32 get_cpu_temp_grade(int *minc, int *maxc)
|
|
|
|
{
|
|
|
|
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
|
|
|
struct fuse_bank *bank = &ocotp->bank[1];
|
|
|
|
struct fuse_bank1_regs *fuse =
|
|
|
|
(struct fuse_bank1_regs *)bank->fuse_regs;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = readl(&fuse->tester3);
|
|
|
|
val >>= OCOTP_TESTER3_TEMP_SHIFT;
|
|
|
|
val &= 0x3;
|
|
|
|
|
|
|
|
if (minc && maxc) {
|
|
|
|
if (val == TEMP_AUTOMOTIVE) {
|
|
|
|
*minc = -40;
|
|
|
|
*maxc = 125;
|
|
|
|
} else if (val == TEMP_INDUSTRIAL) {
|
|
|
|
*minc = -40;
|
|
|
|
*maxc = 105;
|
|
|
|
} else if (val == TEMP_EXTCOMMERCIAL) {
|
|
|
|
*minc = -20;
|
|
|
|
*maxc = 105;
|
|
|
|
} else {
|
|
|
|
*minc = 0;
|
|
|
|
*maxc = 95;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-09-16 03:09:34 +00:00
|
|
|
#if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
|
2018-01-10 05:20:34 +00:00
|
|
|
enum boot_device get_boot_device(void)
|
|
|
|
{
|
|
|
|
struct bootrom_sw_info **p =
|
|
|
|
(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
|
|
|
|
|
|
|
|
enum boot_device boot_dev = SD1_BOOT;
|
|
|
|
u8 boot_type = (*p)->boot_dev_type;
|
|
|
|
u8 boot_instance = (*p)->boot_dev_instance;
|
|
|
|
|
|
|
|
switch (boot_type) {
|
|
|
|
case BOOT_TYPE_SD:
|
|
|
|
boot_dev = boot_instance + SD1_BOOT;
|
|
|
|
break;
|
|
|
|
case BOOT_TYPE_MMC:
|
|
|
|
boot_dev = boot_instance + MMC1_BOOT;
|
|
|
|
break;
|
|
|
|
case BOOT_TYPE_NAND:
|
|
|
|
boot_dev = NAND_BOOT;
|
|
|
|
break;
|
|
|
|
case BOOT_TYPE_QSPI:
|
|
|
|
boot_dev = QSPI_BOOT;
|
|
|
|
break;
|
|
|
|
case BOOT_TYPE_WEIM:
|
|
|
|
boot_dev = WEIM_NOR_BOOT;
|
|
|
|
break;
|
|
|
|
case BOOT_TYPE_SPINOR:
|
|
|
|
boot_dev = SPI_NOR_BOOT;
|
|
|
|
break;
|
2018-11-20 10:19:25 +00:00
|
|
|
#ifdef CONFIG_IMX8M
|
2018-01-10 05:20:35 +00:00
|
|
|
case BOOT_TYPE_USB:
|
|
|
|
boot_dev = USB_BOOT;
|
|
|
|
break;
|
|
|
|
#endif
|
2018-01-10 05:20:34 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return boot_dev;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-11-27 12:25:09 +00:00
|
|
|
#ifdef CONFIG_NXP_BOARD_REVISION
|
|
|
|
int nxp_board_rev(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Get Board ID information from OCOTP_GP1[15:8]
|
|
|
|
* RevA: 0x1
|
|
|
|
* RevB: 0x2
|
|
|
|
* RevC: 0x3
|
|
|
|
*/
|
|
|
|
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
|
|
|
struct fuse_bank *bank = &ocotp->bank[4];
|
|
|
|
struct fuse_bank4_regs *fuse =
|
|
|
|
(struct fuse_bank4_regs *)bank->fuse_regs;
|
|
|
|
|
|
|
|
return (readl(&fuse->gp1) >> 8 & 0x0F);
|
|
|
|
}
|
|
|
|
|
|
|
|
char nxp_board_rev_string(void)
|
|
|
|
{
|
|
|
|
const char *rev = "A";
|
|
|
|
|
|
|
|
return (*rev + nxp_board_rev() - 1);
|
|
|
|
}
|
|
|
|
#endif
|