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u-boot/arch/mips/include/asm/malta.h

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MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:37 +00:00
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
malta: arch/mips/include/asm/malta.h SPDX license tag This patch replaces the GPL-2.0 text with a GPL-2.0 SPDX-License-Identifier tag, and adds Imagination Technologies copyright following my recent changes. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-11 11:03:26 +00:00
* Copyright (C) 2013 Imagination Technologies
MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:37 +00:00
*
malta: arch/mips/include/asm/malta.h SPDX license tag This patch replaces the GPL-2.0 text with a GPL-2.0 SPDX-License-Identifier tag, and adds Imagination Technologies copyright following my recent changes. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-11 11:03:26 +00:00
* SPDX-License-Identifier: GPL-2.0
MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:37 +00:00
*/
#ifndef _MIPS_ASM_MALTA_H
#define _MIPS_ASM_MALTA_H
malta: support for coreFPGA6 boards This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:50 +00:00
#define MALTA_GT_BASE 0x1be00000
#define MALTA_GT_PCIIO_BASE 0x18000000
#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:37 +00:00
malta: support for coreFPGA6 boards This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:50 +00:00
#define MALTA_MSC01_BIU_BASE 0x1bc80000
#define MALTA_MSC01_PCI_BASE 0x1bd00000
#define MALTA_MSC01_PBC_BASE 0x1bd40000
#define MALTA_MSC01_IP1_BASE 0x1bc00000
#define MALTA_MSC01_IP1_SIZE 0x00400000
#define MALTA_MSC01_IP2_BASE1 0x10000000
#define MALTA_MSC01_IP2_SIZE1 0x08000000
#define MALTA_MSC01_IP2_BASE2 0x18000000
#define MALTA_MSC01_IP2_SIZE2 0x04000000
#define MALTA_MSC01_IP3_BASE 0x1c000000
#define MALTA_MSC01_IP3_SIZE 0x04000000
#define MALTA_MSC01_PCIMEM_BASE 0x10000000
#define MALTA_MSC01_PCIMEM_SIZE 0x10000000
#define MALTA_MSC01_PCIMEM_MAP 0x10000000
#define MALTA_MSC01_PCIIO_BASE 0x1b000000
#define MALTA_MSC01_PCIIO_SIZE 0x00800000
#define MALTA_MSC01_PCIIO_MAP 0x00000000
#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8)
MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:37 +00:00
malta: display "U-boot" on the LCD screen Displaying a message on the LCD screen is a simple yet effective way to show the user that the board has booted successfully. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:51 +00:00
#define MALTA_ASCIIWORD 0x1f000410
#define MALTA_ASCIIPOS0 0x1f000418
#define MALTA_ASCIIPOS1 0x1f000420
#define MALTA_ASCIIPOS2 0x1f000428
#define MALTA_ASCIIPOS3 0x1f000430
#define MALTA_ASCIIPOS4 0x1f000438
#define MALTA_ASCIIPOS5 0x1f000440
#define MALTA_ASCIIPOS6 0x1f000448
#define MALTA_ASCIIPOS7 0x1f000450
malta: support for coreFPGA6 boards This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:50 +00:00
#define MALTA_RESET_BASE 0x1f000500
#define GORESET 0x42
MIPS: qemu-malta: setup GT64120 registers as done by YAMON Move the GT64120 register base to 0x1be00000 and setup PCI BAR registers as done by the original YAMON bootloader. This is needed for running Linux kernel. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:41 +00:00
malta: use unmapped flash base address The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range. Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions. Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip. Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants. The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3). Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2013-11-12 15:47:32 +00:00
#define MALTA_FLASH_BASE 0x1e000000
MIPS: qemu-malta: add reset support The MIPS Malta board has a SOFTRES register. Writing a magic value into that register initiates a board reset. Use this feature to implement reset support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:38 +00:00
malta: support for coreFPGA6 boards This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:50 +00:00
#define MALTA_REVISION 0x1fc00010
#define MALTA_REVISION_CORID_SHF 10
#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF)
#define MALTA_REVISION_CORID_CORE_LV 1
#define MALTA_REVISION_CORID_CORE_FPGA6 14
MIPS: qemu-malta: enable flash support Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:39 +00:00
malta: setup PIIX4 interrupt route Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:57 +00:00
#define PCI_CFG_PIIX4_PIRQRCA 0x60
#define PCI_CFG_PIIX4_PIRQRCB 0x61
#define PCI_CFG_PIIX4_PIRQRCC 0x62
#define PCI_CFG_PIIX4_PIRQRCD 0x63
malta: enable PIIX4 SERIRQ Whilst U-boot does not require this itself, Linux currently relies upon it having been muxed and enabled by the bootloader. Thus in order to preserve compatibility with current kernels before a fix is merged in Linux we will enable the SERIRQ interrupt and mux it to its pin. Without doing this current kernels will never receive serial port interrupts and the end result is typically that userland appears to hang. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-26 17:45:27 +00:00
#define PCI_CFG_PIIX4_SERIRQC 0x64
#define PCI_CFG_PIIX4_GENCFG 0xb0
#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
malta: setup PIIX4 interrupt route Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-08 11:18:57 +00:00
MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-05-22 03:57:37 +00:00
#endif /* _MIPS_ASM_MALTA_H */
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