2012-02-07 14:08:48 +00:00
|
|
|
#ifndef _MICREL_H
|
|
|
|
|
|
|
|
#define MII_KSZ9021_EXT_COMMON_CTRL 0x100
|
|
|
|
#define MII_KSZ9021_EXT_STRAP_STATUS 0x101
|
|
|
|
#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
|
|
|
|
#define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
|
|
|
|
#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
|
|
|
|
#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
|
|
|
|
#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
|
|
|
|
#define MII_KSZ9021_EXT_ANALOG_TEST 0x107
|
2013-04-30 14:57:25 +00:00
|
|
|
/* Register operations */
|
|
|
|
#define MII_KSZ9031_MOD_REG 0x0000
|
|
|
|
/* Data operations */
|
|
|
|
#define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
|
|
|
|
#define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000
|
|
|
|
#define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000
|
2012-02-07 14:08:48 +00:00
|
|
|
|
2013-09-02 13:42:28 +00:00
|
|
|
#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4
|
|
|
|
#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
|
|
|
|
#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
|
|
|
|
#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
|
|
|
|
|
2016-10-21 21:31:33 +00:00
|
|
|
#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
|
|
|
|
#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
|
|
|
|
|
2015-07-28 23:24:41 +00:00
|
|
|
/* Registers */
|
|
|
|
#define MMD_ACCESS_CONTROL 0xd
|
|
|
|
#define MMD_ACCESS_REG_DATA 0xe
|
|
|
|
|
2012-02-07 14:08:48 +00:00
|
|
|
struct phy_device;
|
|
|
|
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
|
|
|
|
int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
|
|
|
|
|
2013-04-30 14:57:25 +00:00
|
|
|
int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
|
|
|
|
int regnum, u16 mode, u16 val);
|
|
|
|
int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
|
|
|
|
int regnum, u16 mode);
|
|
|
|
|
2012-02-07 14:08:48 +00:00
|
|
|
#endif
|