2020-09-22 18:45:03 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Writing IntelGraphicsMem table for ACPI
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*
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* Copyright 2019 Google LLC
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* Modified from coreboot src/soc/intel/gma/opregion.h
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*/
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#ifndef _ASM_INTEL_OPREGION_H_
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#define _ASM_INTEL_OPREGION_H_
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#define VBT_SIGNATURE 0x54425624
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/* IGD PCI Configuration register */
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#define ASLS 0xfc /* OpRegion Base */
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#define SWSCI 0xe8 /* SWSCI Register */
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#define SWSMISCI 0xe0 /* SWSMISCI Register */
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#define GSSCIE BIT(0) /* SCI Event trigger */
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#define SMISCISEL BIT(15) /* Select SMI or SCI event source */
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/* mailbox 0: header */
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struct __packed opregion_header {
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u8 signature[16]; /* Offset 0 OpRegion signature */
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u32 size; /* Offset 16 OpRegion size */
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u32 version; /* Offset 20 OpRegion structure version */
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u8 sbios_version[32]; /* Offset 24 System BIOS build version */
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u8 vbios_version[16]; /* Offset 56 Video BIOS build version */
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u8 driver_version[16]; /* Offset 72 Graphic drvr build version */
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u32 mailboxes; /* Offset 88 Mailboxes supported */
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u32 dmod; /* Offset 92 Driver Model */
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u32 pcon; /* Offset 96 Platform Capabilities */
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u16 dver[16]; /* Offset 100 GOP Version */
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u8 reserved[124]; /* Offset 132 Reserved */
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};
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#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
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#define IGD_OPREGION_VERSION 2
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#define IGD_MBOX1 BIT(0)
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#define IGD_MBOX2 BIT(1)
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#define IGD_MBOX3 BIT(2)
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#define IGD_MBOX4 BIT(3)
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#define IGD_MBOX5 BIT(4)
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#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
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IGD_MBOX4 | IGD_MBOX5)
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#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
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#define SBIOS_VERSION_SIZE 32
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/* mailbox 1: public ACPI methods */
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struct __packed opregion_mailbox1 {
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u32 drdy; /* Offset 0 Driver readiness */
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u32 csts; /* Offset 4 Status */
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u32 cevt; /* Offset 8 Current event */
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u8 reserved[20]; /* Offset 12 Reserved */
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u32 didl; /* Offset 32 Supported display device 1 */
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u32 ddl2; /* Offset 36 Supported display device 2 */
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u32 ddl3; /* Offset 40 Supported display device 3 */
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u32 ddl4; /* Offset 44 Supported display device 4 */
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u32 ddl5; /* Offset 48 Supported display device 5 */
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u32 ddl6; /* Offset 52 Supported display device 6 */
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u32 ddl7; /* Offset 56 Supported display device 7 */
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u32 ddl8; /* Offset 60 Supported display device 8 */
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u32 cpdl; /* Offset 64 Currently present display device 1 */
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u32 cpl2; /* Offset 68 Currently present display device 2 */
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u32 cpl3; /* Offset 72 Currently present display device 3 */
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u32 cpl4; /* Offset 76 Currently present display device 4 */
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u32 cpl5; /* Offset 80 Currently present display device 5 */
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u32 cpl6; /* Offset 84 Currently present display device 6 */
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u32 cpl7; /* Offset 88 Currently present display device 7 */
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u32 cpl8; /* Offset 92 Currently present display device 8 */
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u32 cadl; /* Offset 96 Currently active display device 1 */
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u32 cal2; /* Offset 100 Currently active display device 2 */
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u32 cal3; /* Offset 104 Currently active display device 3 */
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u32 cal4; /* Offset 108 Currently active display device 4 */
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u32 cal5; /* Offset 112 Currently active display device 5 */
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u32 cal6; /* Offset 116 Currently active display device 6 */
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u32 cal7; /* Offset 120 Currently active display device 7 */
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u32 cal8; /* Offset 124 Currently active display device 8 */
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u32 nadl; /* Offset 128 Next active device 1 */
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u32 ndl2; /* Offset 132 Next active device 2 */
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u32 ndl3; /* Offset 136 Next active device 3 */
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u32 ndl4; /* Offset 140 Next active device 4 */
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u32 ndl5; /* Offset 144 Next active device 5 */
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u32 ndl6; /* Offset 148 Next active device 6 */
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u32 ndl7; /* Offset 152 Next active device 7 */
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u32 ndl8; /* Offset 156 Next active device 8 */
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u32 aslp; /* Offset 160 ASL sleep timeout */
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u32 tidx; /* Offset 164 Toggle table index */
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u32 chpd; /* Offset 168 Current hot plug enable indicator */
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u32 clid; /* Offset 172 Current lid state indicator */
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u32 cdck; /* Offset 176 Current docking state indicator */
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u32 sxsw; /* Offset 180 Display Switch notification on Sx State
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* resume
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*/
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u32 evts; /* Offset 184 Events supported by ASL */
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u32 cnot; /* Offset 188 Current OS Notification */
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u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */
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u32 ddl9; /* Offset 196 Extended Supported display device 1 */
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u32 dd10; /* Offset 200 Extended Supported display device 2 */
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u32 dd11; /* Offset 204 Extended Supported display device 3 */
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u32 dd12; /* Offset 208 Extended Supported display device 4 */
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u32 dd13; /* Offset 212 Extended Supported display device 5 */
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u32 dd14; /* Offset 216 Extended Supported display device 6 */
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u32 dd15; /* Offset 220 Extended Supported display device 7 */
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u32 cpl9; /* Offset 224 Extended Currently present device 1 */
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u32 cp10; /* Offset 228 Extended Currently present device 2 */
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u32 cp11; /* Offset 232 Extended Currently present device 3 */
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u32 cp12; /* Offset 236 Extended Currently present device 4 */
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u32 cp13; /* Offset 240 Extended Currently present device 5 */
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u32 cp14; /* Offset 244 Extended Currently present device 6 */
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u32 cp15; /* Offset 248 Extended Currently present device 7 */
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u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */
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};
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/* mailbox 2: software sci interface */
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struct __packed opregion_mailbox2 {
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u32 scic; /* Offset 0 Software SCI function number parameters */
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u32 parm; /* Offset 4 Software SCI function number parameters */
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u32 dslp; /* Offset 8 Driver sleep timeout */
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u8 reserved[244]; /* Offset 12 Reserved */
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};
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/* mailbox 3: power conservation */
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struct __packed opregion_mailbox3 {
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u32 ardy; /* Offset 0 Driver readiness */
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u32 aslc; /* Offset 4 ASLE interrupt command / status */
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u32 tche; /* Offset 8 Technology enabled indicator */
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u32 alsi; /* Offset 12 Current ALS illuminance reading */
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u32 bclp; /* Offset 16 Backlight britness to set */
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u32 pfit; /* Offset 20 Panel fitting Request */
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u32 cblv; /* Offset 24 Brightness Current State */
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/* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */
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u16 bclm[20];
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u32 cpfm; /* Offset 68 Panel Fitting Current Mode */
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u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */
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u8 plut[74]; /* Offset 76 Panel Look Up Table */
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/* Offset 150 PWM Frequency and Minimum Brightness */
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u32 pfmb;
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u32 ccdv; /* Offset 154 Color Correction Default Values */
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u32 pcft; /* Offset 158 Power Conservation Features */
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u32 srot; /* Offset 162 Supported Rotation angle */
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u32 iuer; /* Offset 166 Intel Ultrabook Event Register */
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u64 fdsp; /* Offset 170 FFS Display Physical address */
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u32 fdss; /* Offset 178 FFS Display Size */
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u32 stat; /* Offset 182 State Indicator */
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/*
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* Offset 186 (Igd opregion offset 0x3BAh)
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* Physical address of Raw VBT data
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*/
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u64 rvda;
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/* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */
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u32 rvds;
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u8 reserved[58]; /* Offset 198 Reserved */
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};
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#define IGD_BACKLIGHT_BRIGHTNESS 0xff
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#define IGD_INITIAL_BRIGHTNESS 0x64
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#define IGD_FIELD_VALID BIT(31)
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#define IGD_WORD_FIELD_VALID BIT(15)
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#define IGD_PFIT_STRETCH 6
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/* mailbox 4: vbt */
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struct __packed opregion_vbt {
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u8 gvd1[6 << 10];
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};
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/* Mailbox 5: BIOS to Driver Notification Extension */
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struct __packed opregion_mailbox5 {
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u32 phed; /* Offset 7168 Panel Header */
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u8 bddc[256]; /* Offset 7172 Panel EDID */
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u8 reserved[764]; /* Offset 7428 764 bytes */
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};
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/* IGD OpRegion */
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struct __packed igd_opregion {
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struct opregion_header header;
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struct opregion_mailbox1 mailbox1;
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struct opregion_mailbox2 mailbox2;
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struct opregion_mailbox3 mailbox3;
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struct opregion_vbt vbt;
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struct opregion_mailbox5 mailbox5;
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};
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/* Intel Video BIOS (Option ROM) */
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struct __packed optionrom_header {
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u16 signature;
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u8 size;
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u8 reserved[21];
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u16 pcir_offset;
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u16 vbt_offset;
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};
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#define OPROM_SIGNATURE 0xaa55
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struct __packed optionrom_pcir {
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u32 signature;
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u16 vendor;
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u16 device;
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u16 reserved1;
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u16 length;
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u8 revision;
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u8 classcode[3];
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u16 imagelength;
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u16 coderevision;
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u8 codetype;
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u8 indicator;
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u16 reserved2;
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};
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struct __packed optionrom_vbt {
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u8 hdr_signature[20];
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u16 hdr_version;
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u16 hdr_size;
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u16 hdr_vbt_size;
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u8 hdr_vbt_checksum;
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u8 hdr_reserved;
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u32 hdr_vbt_datablock;
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u32 hdr_aim[4];
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u8 datahdr_signature[16];
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u16 datahdr_version;
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u16 datahdr_size;
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u16 datahdr_datablocksize;
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u8 coreblock_id;
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u16 coreblock_size;
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u16 coreblock_biossize;
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u8 coreblock_biostype;
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u8 coreblock_releasestatus;
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u8 coreblock_hwsupported;
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u8 coreblock_integratedhw;
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u8 coreblock_biosbuild[4];
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u8 coreblock_biossignon[155];
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};
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/**
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* intel_gma_init_igd_opregion() - Initialise IGD OpRegion
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*
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* This is called from ACPI code and OS drivers
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*
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2022-01-19 17:05:50 +00:00
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* Return: 0 if OK, -ve on error
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2020-09-22 18:45:03 +00:00
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*/
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int intel_gma_init_igd_opregion(struct udevice *dev,
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struct igd_opregion *opregion);
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#endif /* _ASM_INTEL_OPREGION_H_ */
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