u-boot/arch/xtensa/include/asm/addrspace.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2008-2013 Tensilica Inc.
 * Copyright (C) 2016 Cadence Design Systems Inc.
 */

#ifndef _XTENSA_ADDRSPACE_H
#define _XTENSA_ADDRSPACE_H

#include <asm/arch/core.h>

/*
 * MMU Memory Map
 *
 * noMMU and v3 MMU have identity mapped address space on reset.
 * V2 MMU:
 *   IO (uncached)	f0000000..ffffffff	-> f000000
 *   IO (cached)	e0000000..efffffff	-> f000000
 *   MEM (uncached)	d8000000..dfffffff	-> 0000000
 *   MEM (cached)	d0000000..d7ffffff	-> 0000000
 *
 * The actual location of memory and IO is the board property.
 */

#define IOADDR(x)		(CONFIG_SYS_IO_BASE + (x))
#define MEMADDR(x)		(CONFIG_SYS_MEMORY_BASE + (x))
#define PHYSADDR(x)		((x) - XCHAL_VECBASE_RESET_VADDR + \
				 XCHAL_VECBASE_RESET_PADDR)

#endif	/* _XTENSA_ADDRSPACE_H */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
xtensa: add support for the xtensa processor architecture [2/2] The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> 2016-08-10 15:36:44 +00:00			`/*`
			`* Copyright (C) 2008-2013 Tensilica Inc.`
			`* Copyright (C) 2016 Cadence Design Systems Inc.`
			`*/`

			`#ifndef _XTENSA_ADDRSPACE_H`
			`#define _XTENSA_ADDRSPACE_H`

			`#include <asm/arch/core.h>`

			`/*`
			`* MMU Memory Map`
			`*`
			`* noMMU and v3 MMU have identity mapped address space on reset.`
			`* V2 MMU:`
			`* IO (uncached) f0000000..ffffffff -> f000000`
			`* IO (cached) e0000000..efffffff -> f000000`
			`* MEM (uncached) d8000000..dfffffff -> 0000000`
			`* MEM (cached) d0000000..d7ffffff -> 0000000`
			`*`
			`* The actual location of memory and IO is the board property.`
			`*/`

			`#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x))`
			`#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x))`
			`#define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \`
			`XCHAL_VECBASE_RESET_PADDR)`

			`#endif /* _XTENSA_ADDRSPACE_H */`