2021-04-26 12:53:48 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#ifndef __IMX8MM_ICORE_MX8MM_H
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#define __IMX8MM_ICORE_MX8MM_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_UBOOT_BASE \
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2021-04-26 12:53:48 +00:00
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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2022-12-04 15:04:49 +00:00
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# define CFG_MALLOC_F_ADDR 0x930000
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2021-04-26 12:53:48 +00:00
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/* For RAW image gives a error info not panic */
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#endif /* CONFIG_SPL_BUILD */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 2) \
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func(MMC, mmc, 0)
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#include <config_distro_bootcmd.h>
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#define ENV_MEM_LAYOUT_SETTINGS \
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"fdt_addr_r=0x44000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"ramdisk_addr_r=0x46400000\0" \
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"scriptaddr=0x46000000\0"
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2022-12-04 15:03:50 +00:00
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#define CFG_EXTRA_ENV_SETTINGS \
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2021-04-26 12:53:48 +00:00
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"console=ttymxc1,115200\0" \
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BOOTENV
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/* Link Definitions */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_ADDR 0x40000000
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#define CFG_SYS_INIT_RAM_SIZE SZ_2M
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2021-04-26 12:53:48 +00:00
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0x40000000
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2021-04-26 12:53:48 +00:00
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/* SDRAM configuration */
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
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/* USDHC */
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_USDHC_NUM 2
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#define CFG_SYS_FSL_ESDHC_ADDR 0
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2021-04-26 12:53:48 +00:00
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#endif /* __IMX8MM_ICORE_MX8MM_H */
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