mirror of
https://github.com/AsahiLinux/u-boot
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107 lines
2.5 KiB
C
107 lines
2.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Stefan Roese <sr@denx.de>
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*/
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#include <dm.h>
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#include <ram.h>
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#include <mach/octeon_ddr.h>
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#include <mach/cvmx-qlm.h>
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#include <mach/octeon_qlm.h>
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#include <mach/octeon_fdt.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-cfg.h>
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#include <mach/cvmx-helper-util.h>
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#include <mach/cvmx-bgxx-defs.h>
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#include "board_ddr.h"
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#define NIC23_DEF_DRAM_FREQ 800
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static u8 octeon_nic23_cfg0_spd_values[512] = {
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OCTEON_NIC23_CFG0_SPD_VALUES
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};
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static struct ddr_conf board_ddr_conf[] = {
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OCTEON_NIC23_DDR_CONFIGURATION
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};
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struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
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{
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*count = ARRAY_SIZE(board_ddr_conf);
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*def_ddr_freq = NIC23_DEF_DRAM_FREQ;
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return board_ddr_conf;
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}
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int board_fix_fdt(void *fdt)
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{
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u32 range_data[5 * 8];
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bool rev4;
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int node;
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int rc;
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/*
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* ToDo:
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* Read rev4 info from EEPROM or where the original U-Boot does
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* and don't hard-code it here.
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*/
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rev4 = true;
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debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false");
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/* Patch the PHY configuration based on board revision */
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rc = octeon_fdt_patch_rename(fdt,
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rev4 ? "4,nor-flash" : "4,no-nor-flash",
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"cavium,board-trim", false, NULL, NULL);
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if (!rev4) {
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/* Modify the ranges for CS 0 */
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node = fdt_node_offset_by_compatible(fdt, -1,
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"cavium,octeon-3860-bootbus");
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if (node < 0) {
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printf("%s: Error: cannot find boot bus in device tree!\n",
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__func__);
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return -1;
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}
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rc = fdtdec_get_int_array(fdt, node, "ranges",
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range_data, 5 * 8);
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if (rc) {
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printf("%s: Error reading ranges from boot bus FDT\n",
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__func__);
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return -1;
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}
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range_data[2] = cpu_to_fdt32(0x10000);
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range_data[3] = 0;
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range_data[4] = 0;
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rc = fdt_setprop(fdt, node, "ranges", range_data,
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sizeof(range_data));
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if (rc) {
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printf("%s: Error updating boot bus ranges in fdt\n",
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__func__);
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}
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}
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return rc;
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}
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void board_configure_qlms(void)
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{
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octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0);
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octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0);
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/* Apply amplitude tuning to 10G interface */
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octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1);
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octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1);
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octeon_qlm_set_channel_v3(0, 5, 0);
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octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2);
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debug("QLM 4 reference clock: %d\n"
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"DLM 5 reference clock: %d\n",
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cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5));
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}
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int board_late_init(void)
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{
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board_configure_qlms();
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return 0;
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}
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