2016-06-02 22:10:56 +00:00
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/*
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* Copyright 2013 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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*
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* bcm235xx-specific clock tables
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sysmap.h>
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#include <asm/kona-common/clk.h>
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#include "clk-core.h"
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#define CLOCK_1K 1000
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#define CLOCK_1M (CLOCK_1K * 1000)
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/* declare a reference clock */
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#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
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static struct refclk clk_name = { \
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.clk = { \
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.name = #clk_name, \
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.parent = clk_parent, \
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.rate = clk_rate, \
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.div = clk_div, \
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.ops = &ref_clk_ops, \
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}, \
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}
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/*
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* Reference clocks
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*/
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/* Declare a list of reference clocks */
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DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
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DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
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DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
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DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
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DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
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DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
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DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
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DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
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DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
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DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
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DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
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struct refclk_lkup {
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struct refclk *procclk;
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const char *name;
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};
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/* Lookup table for string to clk tranlation */
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#define MKSTR(x) {&x, #x}
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static struct refclk_lkup refclk_str_tbl[] = {
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MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
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MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
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MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
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MKSTR(var_52m), MKSTR(var_13m),
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};
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int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
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/* convert ref clock string to clock structure pointer */
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struct refclk *refclk_str_to_clk(const char *name)
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{
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int i;
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struct refclk_lkup *tblp = refclk_str_tbl;
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for (i = 0; i < refclk_entries; i++, tblp++) {
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if (!(strcmp(name, tblp->name)))
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return tblp->procclk;
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}
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return NULL;
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}
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/* frequency tables indexed by freq_id */
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unsigned long master_axi_freq_tbl[8] = {
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26 * CLOCK_1M,
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52 * CLOCK_1M,
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104 * CLOCK_1M,
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156 * CLOCK_1M,
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156 * CLOCK_1M,
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208 * CLOCK_1M,
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312 * CLOCK_1M,
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312 * CLOCK_1M
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};
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unsigned long master_ahb_freq_tbl[8] = {
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26 * CLOCK_1M,
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52 * CLOCK_1M,
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52 * CLOCK_1M,
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52 * CLOCK_1M,
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78 * CLOCK_1M,
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104 * CLOCK_1M,
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104 * CLOCK_1M,
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156 * CLOCK_1M
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};
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unsigned long slave_axi_freq_tbl[8] = {
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26 * CLOCK_1M,
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52 * CLOCK_1M,
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78 * CLOCK_1M,
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104 * CLOCK_1M,
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156 * CLOCK_1M,
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156 * CLOCK_1M
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};
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unsigned long slave_apb_freq_tbl[8] = {
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26 * CLOCK_1M,
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26 * CLOCK_1M,
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39 * CLOCK_1M,
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52 * CLOCK_1M,
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52 * CLOCK_1M,
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78 * CLOCK_1M
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};
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unsigned long esub_freq_tbl[8] = {
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78 * CLOCK_1M,
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156 * CLOCK_1M,
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156 * CLOCK_1M,
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156 * CLOCK_1M,
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208 * CLOCK_1M,
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208 * CLOCK_1M,
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208 * CLOCK_1M
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};
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static struct bus_clk_data bsc1_apb_data = {
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.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
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};
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static struct bus_clk_data bsc2_apb_data = {
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.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
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};
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static struct bus_clk_data bsc3_apb_data = {
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.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
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};
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/* * Master CCU clocks */
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static struct peri_clk_data sdio1_data = {
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.gate = HW_SW_GATE(0x0358, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a28, 0, 3),
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.div = DIVIDER(0x0a28, 4, 14),
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.trig = TRIGGER(0x0afc, 9),
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};
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static struct peri_clk_data sdio2_data = {
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.gate = HW_SW_GATE(0x035c, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a2c, 0, 3),
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.div = DIVIDER(0x0a2c, 4, 14),
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.trig = TRIGGER(0x0afc, 10),
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};
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static struct peri_clk_data sdio3_data = {
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.gate = HW_SW_GATE(0x0364, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a34, 0, 3),
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.div = DIVIDER(0x0a34, 4, 14),
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.trig = TRIGGER(0x0afc, 12),
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};
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static struct peri_clk_data sdio4_data = {
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.gate = HW_SW_GATE(0x0360, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a30, 0, 3),
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.div = DIVIDER(0x0a30, 4, 14),
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.trig = TRIGGER(0x0afc, 11),
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};
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static struct peri_clk_data sdio1_sleep_data = {
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.clocks = CLOCKS("ref_32k"),
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.gate = SW_ONLY_GATE(0x0358, 20, 4),
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};
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static struct peri_clk_data sdio2_sleep_data = {
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.clocks = CLOCKS("ref_32k"),
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.gate = SW_ONLY_GATE(0x035c, 20, 4),
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};
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static struct peri_clk_data sdio3_sleep_data = {
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.clocks = CLOCKS("ref_32k"),
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.gate = SW_ONLY_GATE(0x0364, 20, 4),
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};
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static struct peri_clk_data sdio4_sleep_data = {
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.clocks = CLOCKS("ref_32k"),
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.gate = SW_ONLY_GATE(0x0360, 20, 4),
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};
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static struct bus_clk_data usb_otg_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
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};
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static struct bus_clk_data sdio1_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
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};
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static struct bus_clk_data sdio2_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
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};
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static struct bus_clk_data sdio3_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
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};
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static struct bus_clk_data sdio4_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
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};
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/* * Slave CCU clocks */
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static struct peri_clk_data bsc1_data = {
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.gate = HW_SW_GATE(0x0458, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a64, 0, 3),
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.trig = TRIGGER(0x0afc, 23),
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};
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static struct peri_clk_data bsc2_data = {
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.gate = HW_SW_GATE(0x045c, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a68, 0, 3),
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.trig = TRIGGER(0x0afc, 24),
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};
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static struct peri_clk_data bsc3_data = {
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.gate = HW_SW_GATE(0x0484, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a84, 0, 3),
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.trig = TRIGGER(0x0b00, 2),
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};
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/*
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* CCU clocks
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*/
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static struct ccu_clock kpm_ccu_clk = {
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.clk = {
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.name = "kpm_ccu_clk",
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.ops = &ccu_clk_ops,
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.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
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},
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.num_policy_masks = 1,
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.policy_freq_offset = 0x00000008,
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.freq_bit_shift = 8,
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.policy_ctl_offset = 0x0000000c,
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.policy0_mask_offset = 0x00000010,
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.policy1_mask_offset = 0x00000014,
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.policy2_mask_offset = 0x00000018,
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.policy3_mask_offset = 0x0000001c,
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.lvm_en_offset = 0x00000034,
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.freq_id = 2,
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.freq_tbl = master_axi_freq_tbl,
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};
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static struct ccu_clock kps_ccu_clk = {
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.clk = {
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.name = "kps_ccu_clk",
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.ops = &ccu_clk_ops,
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.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
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},
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2016-06-21 23:43:06 +00:00
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.num_policy_masks = 1,
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2016-06-02 22:10:56 +00:00
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.policy_freq_offset = 0x00000008,
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.freq_bit_shift = 8,
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.policy_ctl_offset = 0x0000000c,
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.policy0_mask_offset = 0x00000010,
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.policy1_mask_offset = 0x00000014,
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.policy2_mask_offset = 0x00000018,
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.policy3_mask_offset = 0x0000001c,
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.lvm_en_offset = 0x00000034,
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.freq_id = 2,
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.freq_tbl = slave_axi_freq_tbl,
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};
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#ifdef CONFIG_BCM_SF2_ETH
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static struct ccu_clock esub_ccu_clk = {
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.clk = {
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.name = "esub_ccu_clk",
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.ops = &ccu_clk_ops,
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.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
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},
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.num_policy_masks = 1,
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.policy_freq_offset = 0x00000008,
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.freq_bit_shift = 8,
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.policy_ctl_offset = 0x0000000c,
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.policy0_mask_offset = 0x00000010,
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.policy1_mask_offset = 0x00000014,
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.policy2_mask_offset = 0x00000018,
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.policy3_mask_offset = 0x0000001c,
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.lvm_en_offset = 0x00000034,
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.freq_id = 2,
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.freq_tbl = esub_freq_tbl,
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};
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#endif
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/*
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* Bus clocks
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*/
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/* KPM bus clocks */
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static struct bus_clock usb_otg_ahb_clk = {
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.clk = {
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.name = "usb_otg_ahb_clk",
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.parent = &kpm_ccu_clk.clk,
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.ops = &bus_clk_ops,
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.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
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},
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.freq_tbl = master_ahb_freq_tbl,
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.data = &usb_otg_ahb_data,
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};
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static struct bus_clock sdio1_ahb_clk = {
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.clk = {
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.name = "sdio1_ahb_clk",
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.parent = &kpm_ccu_clk.clk,
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.ops = &bus_clk_ops,
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.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
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},
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|
.freq_tbl = master_ahb_freq_tbl,
|
|
|
|
.data = &sdio1_ahb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct bus_clock sdio2_ahb_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio2_ahb_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.freq_tbl = master_ahb_freq_tbl,
|
|
|
|
.data = &sdio2_ahb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct bus_clock sdio3_ahb_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio3_ahb_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.freq_tbl = master_ahb_freq_tbl,
|
|
|
|
.data = &sdio3_ahb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct bus_clock sdio4_ahb_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio4_ahb_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.freq_tbl = master_ahb_freq_tbl,
|
|
|
|
.data = &sdio4_ahb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct bus_clock bsc1_apb_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "bsc1_apb_clk",
|
|
|
|
.parent = &kps_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.freq_tbl = slave_apb_freq_tbl,
|
|
|
|
.data = &bsc1_apb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct bus_clock bsc2_apb_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "bsc2_apb_clk",
|
|
|
|
.parent = &kps_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.freq_tbl = slave_apb_freq_tbl,
|
|
|
|
.data = &bsc2_apb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct bus_clock bsc3_apb_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "bsc3_apb_clk",
|
|
|
|
.parent = &kps_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.freq_tbl = slave_apb_freq_tbl,
|
|
|
|
.data = &bsc3_apb_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* KPM peripheral */
|
|
|
|
static struct peri_clock sdio1_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio1_clk",
|
|
|
|
.parent = &ref_52m.clk,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio1_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio2_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio2_clk",
|
|
|
|
.parent = &ref_52m.clk,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio2_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio3_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio3_clk",
|
|
|
|
.parent = &ref_52m.clk,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio3_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio4_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio4_clk",
|
|
|
|
.parent = &ref_52m.clk,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio4_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio1_sleep_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio1_sleep_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio1_sleep_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio2_sleep_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio2_sleep_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio2_sleep_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio3_sleep_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio3_sleep_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio3_sleep_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock sdio4_sleep_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "sdio4_sleep_clk",
|
|
|
|
.parent = &kpm_ccu_clk.clk,
|
|
|
|
.ops = &bus_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &sdio4_sleep_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* KPS peripheral clock */
|
|
|
|
static struct peri_clock bsc1_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "bsc1_clk",
|
|
|
|
.parent = &ref_13m.clk,
|
|
|
|
.rate = 13 * CLOCK_1M,
|
|
|
|
.div = 1,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &bsc1_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock bsc2_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "bsc2_clk",
|
|
|
|
.parent = &ref_13m.clk,
|
|
|
|
.rate = 13 * CLOCK_1M,
|
|
|
|
.div = 1,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &bsc2_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clock bsc3_clk = {
|
|
|
|
.clk = {
|
|
|
|
.name = "bsc3_clk",
|
|
|
|
.parent = &ref_13m.clk,
|
|
|
|
.rate = 13 * CLOCK_1M,
|
|
|
|
.div = 1,
|
|
|
|
.ops = &peri_clk_ops,
|
|
|
|
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
|
|
|
},
|
|
|
|
.data = &bsc3_data,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* public table for registering clocks */
|
|
|
|
struct clk_lookup arch_clk_tbl[] = {
|
|
|
|
/* Peripheral clocks */
|
|
|
|
CLK_LK(sdio1),
|
|
|
|
CLK_LK(sdio2),
|
|
|
|
CLK_LK(sdio3),
|
|
|
|
CLK_LK(sdio4),
|
|
|
|
CLK_LK(sdio1_sleep),
|
|
|
|
CLK_LK(sdio2_sleep),
|
|
|
|
CLK_LK(sdio3_sleep),
|
|
|
|
CLK_LK(sdio4_sleep),
|
|
|
|
CLK_LK(bsc1),
|
|
|
|
CLK_LK(bsc2),
|
|
|
|
CLK_LK(bsc3),
|
|
|
|
/* Bus clocks */
|
|
|
|
CLK_LK(usb_otg_ahb),
|
|
|
|
CLK_LK(sdio1_ahb),
|
|
|
|
CLK_LK(sdio2_ahb),
|
|
|
|
CLK_LK(sdio3_ahb),
|
|
|
|
CLK_LK(sdio4_ahb),
|
|
|
|
CLK_LK(bsc1_apb),
|
|
|
|
CLK_LK(bsc2_apb),
|
|
|
|
CLK_LK(bsc3_apb),
|
|
|
|
#ifdef CONFIG_BCM_SF2_ETH
|
|
|
|
CLK_LK(esub_ccu),
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
/* public array size */
|
|
|
|
unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
|