2019-03-13 20:46:41 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
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*/
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/ {
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compatible = "fsl,mcf5282";
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aliases {
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serial0 = &uart0;
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2019-11-15 22:54:12 +00:00
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fec0 = &fec0;
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2019-03-13 20:46:41 +00:00
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ipsbar: ipsbar@4000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x40000000 0x40000000>;
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reg = <0x40000000 0x40000000>;
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2023-06-24 21:38:55 +00:00
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wdog0: watchdog@140000 {
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compatible = "fsl,mcf5282-wdt";
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reg = <0x140000 0x10>;
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status = "disabled";
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};
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2019-03-13 20:46:41 +00:00
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uart0: uart@200 {
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compatible = "fsl,mcf-uart";
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reg = <0x200 0x40>;
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status = "disabled";
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};
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uart1: uart@240 {
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compatible = "fsl,mcf-uart";
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reg = <0x240 0x40>;
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status = "disabled";
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};
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uart2: uart@280 {
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compatible = "fsl,mcf-uart";
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reg = <0x280 0x40>;
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status = "disabled";
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};
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2019-11-15 22:54:12 +00:00
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fec0: ethernet@1000 {
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compatible = "fsl,mcf-fec";
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reg = <0x1000 0x800>;
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mii-base = <0>;
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max-speed = <100>;
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timeout-loop = <50000>;
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status = "disabled";
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};
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2023-04-04 22:59:27 +00:00
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i2c0: i2c@300 {
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compatible = "fsl-i2c";
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#address-cells=<1>;
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#size-cells=<0>;
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cell-index = <0>;
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reg = <0x300 0x14>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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2019-03-13 20:46:41 +00:00
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};
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};
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};
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