mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 13:33:40 +00:00
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
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/*
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* sun50i H616 LPDDR3 timings, as programmed by Allwinner's boot0
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*
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* The chips are probably able to be driven by a faster clock, but boot0
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* uses a more conservative timing (as usual).
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*
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* (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
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* Based on H6 DDR3 timings:
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* (C) Copyright 2018,2019 Arm Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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void mctl_set_timing_params(const struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u8 tccd = 2;
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u8 tfaw = ns_to_t(50);
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u8 trrd = max(ns_to_t(6), 4);
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u8 trcd = ns_to_t(24);
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u8 trc = ns_to_t(70);
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u8 txp = max(ns_to_t(8), 3);
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u8 trtp = max(ns_to_t(8), 2);
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u8 trp = ns_to_t(27);
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u8 tras = ns_to_t(41);
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u16 trefi = ns_to_t(7800) / 64;
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u16 trfc = ns_to_t(210);
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u16 txsr = 88;
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u8 tmrw = 5;
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u8 tmrd = 5;
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u8 tmod = max(ns_to_t(15), 12);
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u8 tcke = max(ns_to_t(6), 3);
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u8 tcksrx = max(ns_to_t(12), 4);
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u8 tcksre = max(ns_to_t(12), 4);
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u8 tckesr = tcke + 2;
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u8 trasmax = (para->clk / 2) / 16;
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u8 txs = ns_to_t(360) / 32;
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u8 txsdll = 16;
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u8 txsabort = 4;
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u8 txsfast = 4;
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u8 tcl = 7;
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u8 tcwl = 4;
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u8 t_rdata_en = 12;
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u8 t_wr_lat = 6;
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u8 twtp = 16;
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u8 twr2rd = trtp + 9;
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u8 trd2wr = 13;
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/* DRAM timing grabbed from tvbox with LPDDR3 memory */
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writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
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&mctl_ctl->dramtmg[0]);
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writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
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writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
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&mctl_ctl->dramtmg[2]);
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writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
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writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
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&mctl_ctl->dramtmg[4]);
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writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
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&mctl_ctl->dramtmg[5]);
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/* Value suggested by ZynqMP manual and used by libdram */
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writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
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writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
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&mctl_ctl->dramtmg[8]);
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writel(0x00020208, &mctl_ctl->dramtmg[9]);
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writel(0xE0C05, &mctl_ctl->dramtmg[10]);
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writel(0x440C021C, &mctl_ctl->dramtmg[11]);
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writel(8, &mctl_ctl->dramtmg[12]);
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writel(0xA100002, &mctl_ctl->dramtmg[13]);
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writel(txsr, &mctl_ctl->dramtmg[14]);
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writel(0x4f0112, &mctl_ctl->init[0]);
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writel(0x420000, &mctl_ctl->init[1]);
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writel(0xd05, &mctl_ctl->init[2]);
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writel(0x83001c, &mctl_ctl->init[3]);
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writel(0x00010000, &mctl_ctl->init[4]);
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writel(0, &mctl_ctl->dfimisc);
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clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
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/* Configure DFI timing */
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writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
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&mctl_ctl->dfitmg0);
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writel(0x100202, &mctl_ctl->dfitmg1);
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/* set refresh timing */
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writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
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}
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