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u-boot/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts

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arm64: zynqmp: Add support for VPXA2785 VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16). Each of the ports can operate in endpoint or root port mode. This allows the single card to be used for both root port, endpoint, and switch modes. The board is designed in the similar manner as others Versal boards. It means board also have ZynqMP Zu4 System Controller which is described in a separate file. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/59d3b1f7e785bc65518b465e5122fd2787616a93.1695808407.git.michal.simek@amd.com
2023-09-27 09:53:35 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
"xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
usb1 = &usb1;
nvmem0 = &eeprom;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0 0 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
j383 {
label = "j383";
gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
linux,code = <BTN_MISC>;
wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
heartbeat-led { /* ds52 */
label = "heartbeat";
gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
si5332_0: si5332_0 { /* ps_ref_clk - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
};
si5332_1: si5332_1 { /* clk0_sgmii - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>; /* FIXME */
};
si5332_2: si5332_2 { /* clk1_usb - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&qspi { /* MIO 0-5 */
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>; /* maybe 4 here */
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
partition@0 { /* for testing purpose */
label = "qspi";
reg = <0 0x4000000>;
};
};
};
&sdhci1 { /* sd MIO 45-51 */
status = "okay";
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
};
&uart0 { /* uart0 MIO38-39 */
status = "okay";
bootph-all;
};
&gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 { /* u131 - M88e1512 */
reg = <0>;
};
};
&gpio {
status = "okay";
gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
"QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
"SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
"", "", "", "", "", /* 15 - 19 */
"", "", "", "", "", /* 20 - 24 */
"", "", "", "", "", /* 25 - 29 */
"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
"SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
"", "", "", "", "", /* 65 - 69 */
"", "", "", "", "", /* 70 - 74 */
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
"", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"", "", "", "", "", /* 110 - 114 */
"", "", "", "", "", /* 115 - 119 */
"", "", "", "", "", /* 120 - 124 */
"", "", "", "", "", /* 125 - 129 */
"", "", "", "", "", /* 130 - 134 */
"", "", "", "", "", /* 135 - 139 */
"", "", "", "", "", /* 140 - 144 */
"", "", "", "", "", /* 145 - 149 */
"", "", "", "", "", /* 150 - 154 */
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller; /* interrupt not connected */
#gpio-cells = <2>;
gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
"", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
"", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
"VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
};
i2c-mux@74 { /* u33 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
pmbus_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* On connector J325 */
reg_vccint: tps53681@60 { /* u266 - 0xc0 */
compatible = "ti,tps53681", "ti,tps53679";
reg = <0x60>;
};
reg_vcc1v1_lp4: tps544@d { /* u85 */
compatible = "ti,tps544b25";
reg = <0xd>;
};
reg_mgtyavcc: tps544@10 { /* u274 */
compatible = "ti,tps544b25";
reg = <0x10>;
};
reg_mgtyavtt: tps544@11 { /* u275 */
compatible = "ti,tps544b25";
reg = <0x11>;
};
reg_vccaux: tps544@12 { /* u276 */
compatible = "ti,tps544b25";
reg = <0x12>;
};
reg_vcc_cpm: tps544@14 { /* u272 */
compatible = "ti,tps544b25";
reg = <0x14>;
};
reg_util_3v3: tps544@1d { /* u278 */
compatible = "ti,tps544b25";
reg = <0x1d>;
};
};
pmbus1_ina226_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* FIXME check alerts coming to SC */
vcc_cpm: ina226@44 { /* u273 */
compatible = "ti,ina226";
reg = <0x44>;
shunt-resistor = <1000>;
};
};
i2c@2 { /* NC */ /* FIXME maybe remove */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
pcie_smbus: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
pcie2_smbus: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { /* NC */
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
user_si570: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
/* 7 unused */
};
};
&i2c1 { /* i2c1 MIO 36-37 */
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { /* u35 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
dc_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* Use for storing information about SC board */
eeprom: eeprom@54 { /* u34 - m24128 16kB */
compatible = "st,24c128", "atmel,24c128";
reg = <0x54>; /* & 0x5c */
};
si570_ref_clk: clock-generator@5d { /* u32 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "ref_clk";
silabs,skip-recall;
};
};
i2c@1 { /* NC - FIXME */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c@2 { /* NC - FIXME */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { /* NC - FIXME */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
lpddr4_si570_clk2_i2c: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
lpddr4_clk2: clock-generator@60 { /* u3 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x60>;
temperature-stability = <50>;
factory-fout = <200000000>;
clock-frequency = <200000000>;
clock-output-names = "lpddr4_clk2";
};
};
lpddr4_si570_clk1_i2c: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
lpddr4_clk1: clock-generator@60 { /* u248 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x60>;
temperature-stability = <50>;
factory-fout = <200000000>;
clock-frequency = <200000000>;
clock-output-names = "lpddr4_clk1";
};
};
/* 6-7 unused */
};
};
&usb0 { /* MIO52 - MIO63 */
status = "okay";
phy-names = "usb3-phy";
phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};
&psgtr {
status = "okay";
/* sgmii, usb3 */
clocks = <&si5332_1>, <&si5332_2>;
clock-names = "ref0", "ref1";
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
maximum-speed = "super-speed";
};
&xilinx_ams {
status = "okay";
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_8_grp";
function = "i2c0";
};
conf {
groups = "i2c0_8_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
mux {
groups = "gpio0_34_grp", "gpio0_35_grp";
function = "gpio0";
};
conf {
groups = "gpio0_34_grp", "gpio0_35_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_9_grp";
function = "i2c1";
};
conf {
groups = "i2c1_9_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_36_grp", "gpio0_37_grp";
function = "gpio0";
};
conf {
groups = "gpio0_36_grp", "gpio0_37_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
};
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