2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2011-04-08 07:10:54 +00:00
|
|
|
/*
|
2013-09-30 09:44:43 +00:00
|
|
|
* Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
|
2011-04-08 07:10:54 +00:00
|
|
|
* Jun-jie Zhang <b18070@freescale.com>
|
|
|
|
* Mingkai Hu <Mingkai.hu@freescale.com>
|
|
|
|
*/
|
2016-01-12 06:41:18 +00:00
|
|
|
|
2011-04-08 07:10:54 +00:00
|
|
|
#include <common.h>
|
|
|
|
#include <miiphy.h>
|
|
|
|
#include <phy.h>
|
|
|
|
#include <fsl_mdio.h>
|
|
|
|
#include <asm/io.h>
|
2016-09-21 02:28:55 +00:00
|
|
|
#include <linux/errno.h>
|
2011-04-08 07:10:54 +00:00
|
|
|
|
2020-04-30 12:59:59 +00:00
|
|
|
#ifdef CONFIG_DM_MDIO
|
|
|
|
struct tsec_mdio_priv {
|
|
|
|
struct tsec_mii_mng __iomem *regs;
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2013-09-30 09:44:43 +00:00
|
|
|
void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
|
2011-04-08 07:10:54 +00:00
|
|
|
int dev_addr, int regnum, int value)
|
|
|
|
{
|
|
|
|
int timeout = 1000000;
|
|
|
|
|
|
|
|
out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
|
|
|
|
out_be32(&phyregs->miimcon, value);
|
2014-09-05 05:52:37 +00:00
|
|
|
/* Memory barrier */
|
|
|
|
mb();
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
2013-09-30 09:44:43 +00:00
|
|
|
int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
|
2011-04-08 07:10:54 +00:00
|
|
|
int dev_addr, int regnum)
|
|
|
|
{
|
|
|
|
int value;
|
|
|
|
int timeout = 1000000;
|
|
|
|
|
2016-01-12 06:41:18 +00:00
|
|
|
/* Put the address of the phy, and the register number into MIIMADD */
|
2011-04-08 07:10:54 +00:00
|
|
|
out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
|
|
|
|
|
|
|
|
/* Clear the command register, and wait */
|
|
|
|
out_be32(&phyregs->miimcom, 0);
|
2014-09-05 05:52:37 +00:00
|
|
|
/* Memory barrier */
|
|
|
|
mb();
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
/* Initiate a read command, and wait */
|
|
|
|
out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
|
2014-09-05 05:52:37 +00:00
|
|
|
/* Memory barrier */
|
|
|
|
mb();
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
/* Wait for the the indication that the read is done */
|
|
|
|
while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
|
|
|
|
&& timeout--)
|
|
|
|
;
|
|
|
|
|
|
|
|
/* Grab the value read from the PHY */
|
|
|
|
value = in_be32(&phyregs->miimstat);
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
2020-04-30 12:59:59 +00:00
|
|
|
#if defined(CONFIG_PHYLIB)
|
2011-04-08 07:10:54 +00:00
|
|
|
static int fsl_pq_mdio_reset(struct mii_dev *bus)
|
|
|
|
{
|
2020-04-30 12:59:59 +00:00
|
|
|
struct tsec_mii_mng __iomem *regs;
|
|
|
|
#ifndef CONFIG_DM_MDIO
|
|
|
|
regs = (struct tsec_mii_mng __iomem *)bus->priv;
|
|
|
|
#else
|
|
|
|
struct tsec_mdio_priv *priv;
|
|
|
|
|
|
|
|
if (!bus->priv)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv = dev_get_priv(bus->priv);
|
|
|
|
regs = priv->regs;
|
|
|
|
#endif
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
/* Reset MII (due to new addresses) */
|
|
|
|
out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT);
|
|
|
|
|
|
|
|
out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
|
|
|
|
|
|
|
|
while (in_be32(®s->miimind) & MIIMIND_BUSY)
|
|
|
|
;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2020-04-30 12:59:59 +00:00
|
|
|
#endif
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
|
|
|
|
{
|
2020-04-30 12:59:59 +00:00
|
|
|
struct tsec_mii_mng __iomem *phyregs;
|
|
|
|
#ifndef CONFIG_DM_MDIO
|
|
|
|
phyregs = (struct tsec_mii_mng __iomem *)bus->priv;
|
|
|
|
#else
|
|
|
|
struct tsec_mdio_priv *priv;
|
|
|
|
|
|
|
|
if (!bus->priv)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv = dev_get_priv(bus->priv);
|
|
|
|
phyregs = priv->regs;
|
|
|
|
#endif
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
|
|
|
|
}
|
|
|
|
|
|
|
|
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
|
|
|
|
u16 value)
|
|
|
|
{
|
2020-04-30 12:59:59 +00:00
|
|
|
struct tsec_mii_mng __iomem *phyregs;
|
|
|
|
#ifndef CONFIG_DM_MDIO
|
|
|
|
phyregs = (struct tsec_mii_mng __iomem *)bus->priv;
|
|
|
|
#else
|
|
|
|
struct tsec_mdio_priv *priv;
|
|
|
|
|
|
|
|
if (!bus->priv)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv = dev_get_priv(bus->priv);
|
|
|
|
phyregs = priv->regs;
|
|
|
|
#endif
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-30 12:59:59 +00:00
|
|
|
#ifndef CONFIG_DM_MDIO
|
2020-06-26 06:13:33 +00:00
|
|
|
int fsl_pq_mdio_init(struct bd_info *bis, struct fsl_pq_mdio_info *info)
|
2011-04-08 07:10:54 +00:00
|
|
|
{
|
|
|
|
struct mii_dev *bus = mdio_alloc();
|
|
|
|
|
|
|
|
if (!bus) {
|
|
|
|
printf("Failed to allocate FSL MDIO bus\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
bus->read = tsec_phy_read;
|
|
|
|
bus->write = tsec_phy_write;
|
|
|
|
bus->reset = fsl_pq_mdio_reset;
|
2015-12-30 13:05:58 +00:00
|
|
|
strcpy(bus->name, info->name);
|
2011-04-08 07:10:54 +00:00
|
|
|
|
2013-09-30 09:44:43 +00:00
|
|
|
bus->priv = (void *)info->regs;
|
2011-04-08 07:10:54 +00:00
|
|
|
|
|
|
|
return mdio_register(bus);
|
|
|
|
}
|
2020-04-30 12:59:59 +00:00
|
|
|
#else /* CONFIG_DM_MDIO */
|
|
|
|
#if defined(CONFIG_PHYLIB)
|
|
|
|
static int tsec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
|
|
|
|
{
|
|
|
|
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
|
|
|
NULL;
|
|
|
|
|
|
|
|
if (pdata && pdata->mii_bus)
|
|
|
|
return tsec_phy_read(pdata->mii_bus, addr, devad, reg);
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsec_mdio_write(struct udevice *dev, int addr, int devad, int reg,
|
|
|
|
u16 val)
|
|
|
|
{
|
|
|
|
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
|
|
|
NULL;
|
|
|
|
|
|
|
|
if (pdata && pdata->mii_bus)
|
|
|
|
return tsec_phy_write(pdata->mii_bus, addr, devad, reg, val);
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsec_mdio_reset(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
|
|
|
NULL;
|
|
|
|
|
|
|
|
if (pdata && pdata->mii_bus)
|
|
|
|
return fsl_pq_mdio_reset(pdata->mii_bus);
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mdio_ops tsec_mdio_ops = {
|
|
|
|
.read = tsec_mdio_read,
|
|
|
|
.write = tsec_mdio_write,
|
|
|
|
.reset = tsec_mdio_reset,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id tsec_mdio_ids[] = {
|
|
|
|
{ .compatible = "fsl,gianfar-tbi" },
|
|
|
|
{ .compatible = "fsl,gianfar-mdio" },
|
|
|
|
{ .compatible = "fsl,etsec2-tbi" },
|
|
|
|
{ .compatible = "fsl,etsec2-mdio" },
|
|
|
|
{ .compatible = "fsl,fman-mdio" },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tsec_mdio_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
|
|
|
|
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
|
|
|
NULL;
|
|
|
|
|
|
|
|
if (!dev) {
|
|
|
|
printf("%s dev = NULL\n", __func__);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
if (!priv) {
|
|
|
|
printf("dev_get_priv(dev %p) = NULL\n", dev);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
|
|
|
|
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
|
|
|
|
priv, priv->regs, pdata);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsec_mdio_remove(struct udevice *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(tsec_mdio) = {
|
|
|
|
.name = "tsec_mdio",
|
|
|
|
.id = UCLASS_MDIO,
|
|
|
|
.of_match = tsec_mdio_ids,
|
|
|
|
.probe = tsec_mdio_probe,
|
|
|
|
.remove = tsec_mdio_remove,
|
|
|
|
.ops = &tsec_mdio_ops,
|
|
|
|
.priv_auto_alloc_size = sizeof(struct tsec_mdio_priv),
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
|
|
|
|
};
|
|
|
|
#endif /* CONFIG_PHYLIB */
|
|
|
|
#endif /* CONFIG_DM_MDIO */
|