u-boot/include/asm-avr32/arch-at32ap700x/memory-map.h

/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __AT32AP7000_MEMORY_MAP_H__
#define __AT32AP7000_MEMORY_MAP_H__

/* Internal and external memories */
#define EBI_SRAM_CS0_BASE			0x00000000
#define EBI_SRAM_CS0_SIZE			0x04000000
#define EBI_SRAM_CS4_BASE			0x04000000
#define EBI_SRAM_CS4_SIZE			0x04000000
#define EBI_SRAM_CS2_BASE			0x08000000
#define EBI_SRAM_CS2_SIZE			0x04000000
#define EBI_SRAM_CS3_BASE			0x0c000000
#define EBI_SRAM_CS3_SIZE			0x04000000
#define EBI_SRAM_CS1_BASE			0x10000000
#define EBI_SRAM_CS1_SIZE			0x10000000
#define EBI_SRAM_CS5_BASE			0x20000000
#define EBI_SRAM_CS5_SIZE			0x04000000

#define EBI_SDRAM_BASE				EBI_SRAM_CS1_BASE
#define EBI_SDRAM_SIZE				EBI_SRAM_CS1_SIZE

#define INTERNAL_SRAM_BASE			0x24000000
#define INTERNAL_SRAM_SIZE			0x00008000

/* Devices on the High Speed Bus (HSB) */
#define LCDC_BASE				0xFF000000
#define DMAC_BASE				0xFF200000
#define USB_FIFO				0xFF300000

/* Devices on Peripheral Bus A (PBA) */
#define SPI0_BASE				0xFFE00000
#define SPI1_BASE				0xFFE00400
#define TWI_BASE				0xFFE00800
#define USART0_BASE				0xFFE00C00
#define USART1_BASE				0xFFE01000
#define USART2_BASE				0xFFE01400
#define USART3_BASE				0xFFE01800
#define SSC0_BASE				0xFFE01C00
#define SSC1_BASE				0xFFE02000
#define SSC2_BASE				0xFFE02400
#define PIOA_BASE				0xFFE02800
#define PIOB_BASE				0xFFE02C00
#define PIOC_BASE				0xFFE03000
#define PIOD_BASE				0xFFE03400
#define PIOE_BASE				0xFFE03800
#define PSIF_BASE				0xFFE03C00

/* Devices on Peripheral Bus B (PBB) */
#define SM_BASE					0xFFF00000
#define INTC_BASE				0xFFF00400
#define HMATRIX_BASE				0xFFF00800
#define TIMER0_BASE				0xFFF00C00
#define TIMER1_BASE				0xFFF01000
#define PWM_BASE				0xFFF01400
#define MACB0_BASE				0xFFF01800
#define MACB1_BASE				0xFFF01C00
#define DAC_BASE				0xFFF02000
#define MMCI_BASE				0xFFF02400
#define AUDIOC_BASE				0xFFF02800
#define HISI_BASE				0xFFF02C00
#define USB_BASE				0xFFF03000
#define HSMC_BASE				0xFFF03400
#define HSDRAMC_BASE				0xFFF03800
#define ECC_BASE				0xFFF03C00

#endif /* __AT32AP7000_MEMORY_MAP_H__ */
Add AT32AP CPU and AT32AP7000 SoC support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> 2006-10-24 12:27:35 +00:00			`/*`
			`* Copyright (C) 2005-2006 Atmel Corporation`
			`*`
			`* See file CREDITS for list of people who contributed to this`
			`* project.`
			`*`
			`* This program is free software; you can redistribute it and/or`
			`* modify it under the terms of the GNU General Public License as`
			`* published by the Free Software Foundation; either version 2 of`
			`* the License, or (at your option) any later version.`
			`*`
			`* This program is distributed in the hope that it will be useful,`
			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
			`* GNU General Public License for more details.`
			`*`
			`* You should have received a copy of the GNU General Public License`
			`* along with this program; if not, write to the Free Software`
			`* Foundation, Inc., 59 Temple Place, Suite 330, Boston,`
			`* MA 02111-1307 USA`
			`*/`
AVR32: Clean up memory-map.h for at32ap7000 Convert spaces to tabs (must have missed this one last time around), sort the entries by address and group them together by bus connectivity. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> 2006-11-18 17:01:13 +00:00			`#ifndef __AT32AP7000_MEMORY_MAP_H__`
			`#define __AT32AP7000_MEMORY_MAP_H__`
Add AT32AP CPU and AT32AP7000 SoC support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> 2006-10-24 12:27:35 +00:00
avr32: Rework SDRAM initialization code This cleans up the SDRAM initialization and related code a bit, and allows faster booting. * Add definitions for EBI and internal SRAM to asm/arch/memory-map.h * Remove memory test from sdram_init() and make caller responsible for verifying the SDRAM and determining its size. * Remove base_address member from struct sdram_config (was sdram_info) * Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT * Add support for a common STK1000 hack: 16MB SDRAM instead of 8. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 2008-05-19 09:36:28 +00:00			`/* Internal and external memories */`
			`#define EBI_SRAM_CS0_BASE 0x00000000`
			`#define EBI_SRAM_CS0_SIZE 0x04000000`
			`#define EBI_SRAM_CS4_BASE 0x04000000`
			`#define EBI_SRAM_CS4_SIZE 0x04000000`
			`#define EBI_SRAM_CS2_BASE 0x08000000`
			`#define EBI_SRAM_CS2_SIZE 0x04000000`
			`#define EBI_SRAM_CS3_BASE 0x0c000000`
			`#define EBI_SRAM_CS3_SIZE 0x04000000`
			`#define EBI_SRAM_CS1_BASE 0x10000000`
			`#define EBI_SRAM_CS1_SIZE 0x10000000`
			`#define EBI_SRAM_CS5_BASE 0x20000000`
			`#define EBI_SRAM_CS5_SIZE 0x04000000`

			`#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE`
			`#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE`

			`#define INTERNAL_SRAM_BASE 0x24000000`
			`#define INTERNAL_SRAM_SIZE 0x00008000`

AVR32: Clean up memory-map.h for at32ap7000 Convert spaces to tabs (must have missed this one last time around), sort the entries by address and group them together by bus connectivity. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> 2006-11-18 17:01:13 +00:00			`/* Devices on the High Speed Bus (HSB) */`
			`#define LCDC_BASE 0xFF000000`
			`#define DMAC_BASE 0xFF200000`
			`#define USB_FIFO 0xFF300000`
Add AT32AP CPU and AT32AP7000 SoC support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> 2006-10-24 12:27:35 +00:00
AVR32: Clean up memory-map.h for at32ap7000 Convert spaces to tabs (must have missed this one last time around), sort the entries by address and group them together by bus connectivity. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> 2006-11-18 17:01:13 +00:00			`/* Devices on Peripheral Bus A (PBA) */`
			`#define SPI0_BASE 0xFFE00000`
			`#define SPI1_BASE 0xFFE00400`
			`#define TWI_BASE 0xFFE00800`
			`#define USART0_BASE 0xFFE00C00`
			`#define USART1_BASE 0xFFE01000`
			`#define USART2_BASE 0xFFE01400`
			`#define USART3_BASE 0xFFE01800`
			`#define SSC0_BASE 0xFFE01C00`
			`#define SSC1_BASE 0xFFE02000`
			`#define SSC2_BASE 0xFFE02400`
			`#define PIOA_BASE 0xFFE02800`
			`#define PIOB_BASE 0xFFE02C00`
			`#define PIOC_BASE 0xFFE03000`
			`#define PIOD_BASE 0xFFE03400`
			`#define PIOE_BASE 0xFFE03800`
			`#define PSIF_BASE 0xFFE03C00`

			`/* Devices on Peripheral Bus B (PBB) */`
			`#define SM_BASE 0xFFF00000`
			`#define INTC_BASE 0xFFF00400`
			`#define HMATRIX_BASE 0xFFF00800`
			`#define TIMER0_BASE 0xFFF00C00`
			`#define TIMER1_BASE 0xFFF01000`
			`#define PWM_BASE 0xFFF01400`
			`#define MACB0_BASE 0xFFF01800`
			`#define MACB1_BASE 0xFFF01C00`
			`#define DAC_BASE 0xFFF02000`
			`#define MMCI_BASE 0xFFF02400`
			`#define AUDIOC_BASE 0xFFF02800`
			`#define HISI_BASE 0xFFF02C00`
			`#define USB_BASE 0xFFF03000`
			`#define HSMC_BASE 0xFFF03400`
			`#define HSDRAMC_BASE 0xFFF03800`
			`#define ECC_BASE 0xFFF03C00`

			`#endif /* __AT32AP7000_MEMORY_MAP_H__ */`