2007-07-27 12:43:59 +00:00
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/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
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* Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Based on the MPC83xx code.
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*/
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/*
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* U-Boot - Startup Code for MPC512x based Embedded Boards
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*/
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#include <config.h>
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#include <mpc512x.h>
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2008-11-03 15:30:59 +00:00
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#include <timestamp.h>
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2007-07-27 12:43:59 +00:00
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#include <version.h>
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#define CONFIG_521X 1 /* needed for Linux kernel header files*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING "MPC512X"
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#endif
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/*
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* Floating Point enable, Machine Check and Recoverable Interr.
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*/
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#undef MSR_KERNEL
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#ifdef DEBUG
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#define MSR_KERNEL (MSR_FP|MSR_RI)
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#else
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#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
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#endif
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/* Macros for manipulating CSx_START/STOP */
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#define START_REG(start) ((start) >> 16)
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#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r14 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* Magic number and version string
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*/
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.long 0x27051956 /* U-Boot Magic Number */
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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2008-11-03 15:30:59 +00:00
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.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
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2007-07-27 12:43:59 +00:00
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.ascii " ", CONFIG_IDENT_STRING, "\0"
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/*
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* Vector Table
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*/
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.text
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. = EXC_OFF_SYS_RESET
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.globl _start
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/* Start from here after reset/power on */
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_start:
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li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
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b boot_cold
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.globl _start_of_vectors
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_start_of_vectors:
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/* Machine check */
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STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Floating Point Unit unavailable exception */
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* Decrementer */
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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/* Critical interrupt */
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STD_EXCEPTION(0xa00, Critical, UnknownException)
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/* System Call */
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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/* Trace interrupt */
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STD_EXCEPTION(0xd00, Trace, UnknownException)
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/* Performance Monitor interrupt */
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STD_EXCEPTION(0xf00, PerfMon, UnknownException)
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/* Intruction Translation Miss */
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STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
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/* Data Load Translation Miss */
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STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
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/* Data Store Translation Miss */
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STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
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/* Instruction Address Breakpoint */
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STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
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/* System Management interrupt */
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STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x3000
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boot_cold:
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/* Save msr contents */
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mfmsr r5
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/* Set IMMR area to our preferred location */
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lis r4, CONFIG_DEFAULT_IMMR@h
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2008-10-16 13:01:15 +00:00
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lis r3, CONFIG_SYS_IMMR@h
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ori r3, r3, CONFIG_SYS_IMMR@l
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2007-07-27 12:43:59 +00:00
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stw r3, IMMRBAR(r4)
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mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
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/* Initialise the machine */
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bl cpu_early_init
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/*
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* Set up Local Access Windows:
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*
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* 1) Boot/CS0 (boot FLASH)
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* 2) On-chip SRAM (initial stack purposes)
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*/
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/* Boot CS/CS0 window range */
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2008-10-16 13:01:15 +00:00
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lis r3, CONFIG_SYS_IMMR@h
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ori r3, r3, CONFIG_SYS_IMMR@l
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2007-07-27 12:43:59 +00:00
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2008-10-16 13:01:15 +00:00
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lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
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ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
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2007-07-27 12:43:59 +00:00
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stw r4, LPCS0AW(r3)
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/*
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* The SRAM window has a fixed size (256K), so only the start address
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* is necessary
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*/
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2008-10-16 13:01:15 +00:00
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lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
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2007-07-27 12:43:59 +00:00
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stw r4, SRAMBAR(r3)
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2007-08-02 19:27:46 +00:00
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/*
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2007-07-27 12:43:59 +00:00
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* According to MPC5121e RM, configuring local access windows should
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2007-08-02 19:27:46 +00:00
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* be followed by a dummy read of the config register that was
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2007-07-27 12:43:59 +00:00
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* modified last and an isync
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2007-08-02 19:27:46 +00:00
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*/
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2007-07-27 12:43:59 +00:00
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lwz r4, SRAMBAR(r3)
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isync
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/*
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* Set configuration of the Boot/CS0, the SRAM window does not have a
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* config register so no params can be set for it
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*/
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2008-10-16 13:01:15 +00:00
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lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
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ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
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2007-07-27 12:43:59 +00:00
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2008-10-16 13:01:15 +00:00
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lis r4, CONFIG_SYS_CS0_CFG@h
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ori r4, r4, CONFIG_SYS_CS0_CFG@l
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2007-08-02 19:27:46 +00:00
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stw r4, CS0_CONFIG(r3)
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2007-07-27 12:43:59 +00:00
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/* Master enable all CS's */
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lis r4, CS_CTRL_ME@h
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ori r4, r4, CS_CTRL_ME@l
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stw r4, CS_CTRL(r3)
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2008-10-16 13:01:15 +00:00
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lis r4, (CONFIG_SYS_MONITOR_BASE)@h
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ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
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2007-07-27 12:43:59 +00:00
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addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
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mtlr r5
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blr
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in_flash:
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2008-10-16 13:01:15 +00:00
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lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
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ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
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2007-07-27 12:43:59 +00:00
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/* let the C-code set up the rest */
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/* */
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/* Be careful to keep code relocatable & stack humble */
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/*------------------------------------------------------*/
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GET_GOT /* initialize GOT access */
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/* r3: IMMR */
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2008-10-16 13:01:15 +00:00
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lis r3, CONFIG_SYS_IMMR@h
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2007-07-27 12:43:59 +00:00
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/* run low-level CPU init code (in Flash) */
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bl cpu_init_f
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/* r3: BOOTFLAG */
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mr r3, r21
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/* run 1st part of board init code (in Flash) */
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bl board_init_f
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/* NOTREACHED - board_init_f() does not return */
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/*
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* This code finishes saving the registers to the exception frame
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* and jumps to the appropriate handler for the exception.
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* Register r21 is pointer into trap frame, r1 has new stack pointer.
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*/
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.globl transfer_to_handler
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transfer_to_handler:
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stw r22,_NIP(r21)
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lis r22,MSR_POW@h
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andc r23,r23,r22
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stw r23,_MSR(r21)
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SAVE_GPR(7, r21)
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SAVE_4GPRS(8, r21)
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SAVE_8GPRS(12, r21)
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SAVE_8GPRS(24, r21)
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mflr r23
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andi. r24,r23,0x3f00 /* get vector offset */
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stw r24,TRAP(r21)
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li r22,0
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stw r22,RESULT(r21)
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lwz r24,0(r23) /* virtual address of handler */
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lwz r23,4(r23) /* where to go when done */
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mtspr SRR0,r24
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mtspr SRR1,r20
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mtlr r23
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SYNC
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rfi /* jump to handler, enable MMU */
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int_return:
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mfmsr r28 /* Disable interrupts */
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li r4,0
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ori r4,r4,MSR_EE
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andc r28,r28,r4
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SYNC /* Some chip revs need this... */
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mtmsr r28
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SYNC
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lwz r2,_CTR(r1)
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lwz r0,_LINK(r1)
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mtctr r2
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mtlr r0
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lwz r2,_XER(r1)
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lwz r0,_CCR(r1)
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mtspr XER,r2
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mtcrf 0xFF,r0
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REST_10GPRS(3, r1)
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REST_10GPRS(13, r1)
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REST_8GPRS(23, r1)
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REST_GPR(31, r1)
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lwz r2,_NIP(r1) /* Restore environment */
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lwz r0,_MSR(r1)
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mtspr SRR0,r2
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mtspr SRR1,r0
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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SYNC
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rfi
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/*
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* This code initialises the machine, it expects original MSR contents to be in r5.
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*/
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cpu_early_init:
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/* Initialize machine status; enable machine check interrupt */
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/*-----------------------------------------------------------*/
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li r3, MSR_KERNEL /* Set ME and RI flags */
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rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
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#ifdef DEBUG
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|
|
|
rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
|
|
|
|
#endif
|
|
|
|
mtmsr r3
|
|
|
|
SYNC
|
|
|
|
mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3, CONFIG_SYS_IMMR@h
|
2007-07-27 12:43:59 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_WATCHDOG)
|
|
|
|
/* Initialise the watchdog and reset it */
|
|
|
|
/*--------------------------------------*/
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r4, CONFIG_SYS_WATCHDOG_VALUE
|
2007-07-27 12:43:59 +00:00
|
|
|
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
|
|
|
|
stw r4, SWCRR(r3)
|
|
|
|
|
|
|
|
/* reset */
|
|
|
|
li r4, 0x556C
|
|
|
|
sth r4, SWSRR@l(r3)
|
|
|
|
li r4, 0x0
|
|
|
|
ori r4, r4, 0xAA39
|
|
|
|
sth r4, SWSRR@l(r3)
|
|
|
|
#else
|
|
|
|
/* Disable the watchdog */
|
|
|
|
/*----------------------*/
|
|
|
|
lwz r4, SWCRR(r3)
|
|
|
|
/*
|
|
|
|
* Check to see if it's enabled for disabling: once disabled by s/w
|
|
|
|
* it's not possible to re-enable it
|
|
|
|
*/
|
|
|
|
andi. r4, r4, 0x4
|
|
|
|
beq 1f
|
|
|
|
xor r4, r4, r4
|
|
|
|
stw r4, SWCRR(r3)
|
|
|
|
1:
|
|
|
|
#endif /* CONFIG_WATCHDOG */
|
|
|
|
|
|
|
|
/* Initialize the Hardware Implementation-dependent Registers */
|
|
|
|
/* HID0 also contains cache control */
|
|
|
|
/*------------------------------------------------------*/
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3, CONFIG_SYS_HID0_INIT@h
|
|
|
|
ori r3, r3, CONFIG_SYS_HID0_INIT@l
|
2007-07-27 12:43:59 +00:00
|
|
|
SYNC
|
|
|
|
mtspr HID0, r3
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3, CONFIG_SYS_HID0_FINAL@h
|
|
|
|
ori r3, r3, CONFIG_SYS_HID0_FINAL@l
|
2007-07-27 12:43:59 +00:00
|
|
|
SYNC
|
|
|
|
mtspr HID0, r3
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3, CONFIG_SYS_HID2@h
|
|
|
|
ori r3, r3, CONFIG_SYS_HID2@l
|
2007-07-27 12:43:59 +00:00
|
|
|
SYNC
|
|
|
|
mtspr HID2, r3
|
|
|
|
sync
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
|
|
/* Cache functions.
|
|
|
|
*
|
|
|
|
* Note: requires that all cache bits in
|
|
|
|
* HID0 are in the low half word.
|
|
|
|
*/
|
|
|
|
.globl icache_enable
|
|
|
|
icache_enable:
|
|
|
|
mfspr r3, HID0
|
|
|
|
ori r3, r3, HID0_ICE
|
|
|
|
lis r4, 0
|
|
|
|
ori r4, r4, HID0_ILOCK
|
|
|
|
andc r3, r3, r4
|
|
|
|
ori r4, r3, HID0_ICFI
|
|
|
|
isync
|
|
|
|
mtspr HID0, r4 /* sets enable and invalidate, clears lock */
|
|
|
|
isync
|
|
|
|
mtspr HID0, r3 /* clears invalidate */
|
|
|
|
blr
|
|
|
|
|
|
|
|
.globl icache_disable
|
|
|
|
icache_disable:
|
|
|
|
mfspr r3, HID0
|
|
|
|
lis r4, 0
|
|
|
|
ori r4, r4, HID0_ICE|HID0_ILOCK
|
|
|
|
andc r3, r3, r4
|
|
|
|
ori r4, r3, HID0_ICFI
|
|
|
|
isync
|
|
|
|
mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
|
|
|
|
isync
|
|
|
|
mtspr HID0, r3 /* clears invalidate */
|
|
|
|
blr
|
|
|
|
|
|
|
|
.globl icache_status
|
|
|
|
icache_status:
|
|
|
|
mfspr r3, HID0
|
|
|
|
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
|
|
|
|
blr
|
|
|
|
|
|
|
|
.globl dcache_enable
|
|
|
|
dcache_enable:
|
|
|
|
mfspr r3, HID0
|
|
|
|
li r5, HID0_DCFI|HID0_DLOCK
|
|
|
|
andc r3, r3, r5
|
|
|
|
mtspr HID0, r3 /* no invalidate, unlock */
|
|
|
|
ori r3, r3, HID0_DCE
|
|
|
|
ori r5, r3, HID0_DCFI
|
|
|
|
mtspr HID0, r5 /* enable + invalidate */
|
|
|
|
mtspr HID0, r3 /* enable */
|
|
|
|
sync
|
|
|
|
blr
|
|
|
|
|
|
|
|
.globl dcache_disable
|
|
|
|
dcache_disable:
|
|
|
|
mfspr r3, HID0
|
|
|
|
lis r4, 0
|
|
|
|
ori r4, r4, HID0_DCE|HID0_DLOCK
|
|
|
|
andc r3, r3, r4
|
|
|
|
ori r4, r3, HID0_DCI
|
|
|
|
sync
|
|
|
|
mtspr HID0, r4 /* sets invalidate, clears enable and lock */
|
|
|
|
sync
|
|
|
|
mtspr HID0, r3 /* clears invalidate */
|
|
|
|
blr
|
|
|
|
|
|
|
|
.globl dcache_status
|
|
|
|
dcache_status:
|
|
|
|
mfspr r3, HID0
|
|
|
|
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
|
|
|
|
blr
|
|
|
|
|
|
|
|
.globl get_pvr
|
|
|
|
get_pvr:
|
|
|
|
mfspr r3, PVR
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* void relocate_code (addr_sp, gd, addr_moni)
|
|
|
|
*
|
|
|
|
* This "function" does not return, instead it continues in RAM
|
|
|
|
* after relocating the monitor code.
|
|
|
|
*
|
|
|
|
* r3 = dest
|
|
|
|
* r4 = src
|
|
|
|
* r5 = length in bytes
|
|
|
|
* r6 = cachelinesize
|
|
|
|
*/
|
|
|
|
.globl relocate_code
|
|
|
|
relocate_code:
|
|
|
|
mr r1, r3 /* Set new stack pointer */
|
|
|
|
mr r9, r4 /* Save copy of Global Data pointer */
|
|
|
|
mr r10, r5 /* Save copy of Destination Address */
|
|
|
|
|
|
|
|
mr r3, r5 /* Destination Address */
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
|
|
|
|
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
|
2007-07-27 12:43:59 +00:00
|
|
|
lwz r5, GOT(__init_end)
|
|
|
|
sub r5, r5, r4
|
2008-10-16 13:01:15 +00:00
|
|
|
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
|
2007-07-27 12:43:59 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Fix GOT pointer:
|
|
|
|
*
|
2008-10-16 13:01:15 +00:00
|
|
|
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
|
2007-07-27 12:43:59 +00:00
|
|
|
* + Destination Address
|
|
|
|
*
|
|
|
|
* Offset:
|
|
|
|
*/
|
|
|
|
sub r15, r10, r4
|
|
|
|
|
|
|
|
/* First our own GOT */
|
|
|
|
add r14, r14, r15
|
|
|
|
/* then the one used by the C code */
|
|
|
|
add r30, r30, r15
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now relocate code
|
|
|
|
*/
|
|
|
|
cmplw cr1,r3,r4
|
|
|
|
addi r0,r5,3
|
|
|
|
srwi. r0,r0,2
|
|
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
|
|
beq 7f /* Protect against 0 count */
|
|
|
|
mtctr r0
|
|
|
|
bge cr1,2f
|
|
|
|
la r8,-4(r4)
|
|
|
|
la r7,-4(r3)
|
|
|
|
|
|
|
|
/* copy */
|
|
|
|
1: lwzu r0,4(r8)
|
|
|
|
stwu r0,4(r7)
|
|
|
|
bdnz 1b
|
|
|
|
|
|
|
|
addi r0,r5,3
|
|
|
|
srwi. r0,r0,2
|
|
|
|
mtctr r0
|
|
|
|
la r8,-4(r4)
|
|
|
|
la r7,-4(r3)
|
|
|
|
|
|
|
|
/* and compare */
|
|
|
|
20: lwzu r20,4(r8)
|
|
|
|
lwzu r21,4(r7)
|
|
|
|
xor. r22, r20, r21
|
|
|
|
bne 30f
|
|
|
|
bdnz 20b
|
|
|
|
b 4f
|
|
|
|
|
|
|
|
/* compare failed */
|
|
|
|
30: li r3, 0
|
|
|
|
blr
|
|
|
|
|
|
|
|
2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
|
|
|
|
add r8,r4,r0
|
|
|
|
add r7,r3,r0
|
|
|
|
3: lwzu r0,-4(r8)
|
|
|
|
stwu r0,-4(r7)
|
|
|
|
bdnz 3b
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
|
|
* address. Otherwise we might miss one cache line.
|
|
|
|
*/
|
|
|
|
4: cmpwi r6,0
|
|
|
|
add r5,r3,r5
|
|
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
|
|
subi r0,r6,1
|
|
|
|
andc r3,r3,r0
|
|
|
|
mr r4,r3
|
|
|
|
5: dcbst 0,r4
|
|
|
|
add r4,r4,r6
|
|
|
|
cmplw r4,r5
|
|
|
|
blt 5b
|
|
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
|
|
mr r4,r3
|
|
|
|
6: icbi 0,r4
|
|
|
|
add r4,r4,r6
|
|
|
|
cmplw r4,r5
|
|
|
|
blt 6b
|
|
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
|
|
isync
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We are done. Do not return, instead branch to second part of board
|
|
|
|
* initialization, now running from RAM.
|
|
|
|
*/
|
|
|
|
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
|
|
mtlr r0
|
|
|
|
blr
|
|
|
|
|
|
|
|
in_ram:
|
|
|
|
/*
|
|
|
|
* Relocation Function, r14 point to got2+0x8000
|
|
|
|
*
|
|
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
|
|
* already puts a few entries in the table.
|
|
|
|
*/
|
|
|
|
li r0,__got2_entries@sectoff@l
|
|
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
|
|
mtctr r0
|
|
|
|
sub r11,r3,r11
|
|
|
|
addi r3,r3,-4
|
|
|
|
1: lwzu r0,4(r3)
|
|
|
|
add r0,r0,r11
|
|
|
|
stw r0,0(r3)
|
|
|
|
bdnz 1b
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
|
|
* in case we need to move ourselves again.
|
|
|
|
*/
|
|
|
|
2: li r0,__fixup_entries@sectoff@l
|
|
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
|
|
cmpwi r0,0
|
|
|
|
mtctr r0
|
|
|
|
addi r3,r3,-4
|
|
|
|
beq 4f
|
|
|
|
3: lwzu r4,4(r3)
|
|
|
|
lwzux r0,r4,r11
|
|
|
|
add r0,r0,r11
|
|
|
|
stw r10,0(r3)
|
|
|
|
stw r0,0(r4)
|
|
|
|
bdnz 3b
|
|
|
|
4:
|
|
|
|
clear_bss:
|
|
|
|
/*
|
|
|
|
* Now clear BSS segment
|
|
|
|
*/
|
|
|
|
lwz r3,GOT(__bss_start)
|
|
|
|
lwz r4,GOT(_end)
|
|
|
|
|
|
|
|
cmplw 0, r3, r4
|
|
|
|
beq 6f
|
|
|
|
|
|
|
|
li r0, 0
|
|
|
|
5:
|
|
|
|
stw r0, 0(r3)
|
|
|
|
addi r3, r3, 4
|
|
|
|
cmplw 0, r3, r4
|
|
|
|
bne 5b
|
|
|
|
6:
|
|
|
|
mr r3, r9 /* Global Data pointer */
|
|
|
|
mr r4, r10 /* Destination Address */
|
|
|
|
bl board_init_r
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Copy exception vector code to low memory
|
|
|
|
*
|
|
|
|
* r3: dest_addr
|
|
|
|
* r7: source address, r8: end address, r9: target address
|
|
|
|
*/
|
|
|
|
.globl trap_init
|
|
|
|
trap_init:
|
|
|
|
lwz r7, GOT(_start)
|
|
|
|
lwz r8, GOT(_end_of_vectors)
|
|
|
|
|
|
|
|
li r9, 0x100 /* reset vector at 0x100 */
|
|
|
|
|
|
|
|
cmplw 0, r7, r8
|
|
|
|
bgelr /* return if r7>=r8 - just in case */
|
|
|
|
|
|
|
|
mflr r4 /* save link register */
|
|
|
|
1:
|
|
|
|
lwz r0, 0(r7)
|
|
|
|
stw r0, 0(r9)
|
|
|
|
addi r7, r7, 4
|
|
|
|
addi r9, r9, 4
|
|
|
|
cmplw 0, r7, r8
|
|
|
|
bne 1b
|
|
|
|
|
|
|
|
/*
|
|
|
|
* relocate `hdlr' and `int_return' entries
|
|
|
|
*/
|
|
|
|
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
|
|
|
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
|
|
|
2:
|
|
|
|
bl trap_reloc
|
|
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
|
|
cmplw 0, r7, r8
|
|
|
|
blt 2b
|
|
|
|
|
|
|
|
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
|
|
|
bl trap_reloc
|
|
|
|
|
|
|
|
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
|
|
|
bl trap_reloc
|
|
|
|
|
|
|
|
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
|
|
|
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
|
|
|
3:
|
|
|
|
bl trap_reloc
|
|
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
|
|
cmplw 0, r7, r8
|
|
|
|
blt 3b
|
|
|
|
|
|
|
|
li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
|
|
|
|
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
|
|
4:
|
|
|
|
bl trap_reloc
|
|
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
|
|
cmplw 0, r7, r8
|
|
|
|
blt 4b
|
|
|
|
|
|
|
|
mfmsr r3 /* now that the vectors have */
|
|
|
|
lis r7, MSR_IP@h /* relocated into low memory */
|
|
|
|
ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
|
|
|
|
andc r3, r3, r7 /* (if it was on) */
|
|
|
|
SYNC /* Some chip revs need this... */
|
|
|
|
mtmsr r3
|
|
|
|
SYNC
|
|
|
|
|
|
|
|
mtlr r4 /* restore link register */
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/*
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* Function: relocate entries for one exception vector
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*/
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trap_reloc:
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lwz r0, 0(r7) /* hdlr ... */
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add r0, r0, r3 /* ... += dest_addr */
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stw r0, 0(r7)
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lwz r0, 4(r7) /* int_return ... */
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add r0, r0, r3 /* ... += dest_addr */
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stw r0, 4(r7)
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