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23 lines
515 B
Text
23 lines
515 B
Text
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gdsys AXI busses of IHS FPGA devices
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Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which
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the connected devices (usually IP cores) can be controlled via software.
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Required properties:
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- compatible: must be "gdsys,ihs_axi"
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- reg: describes the address and length of the AXI bus's register map (within
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the FPGA's register space)
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Example:
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fpga0_axi_video0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "gdsys,ihs_axi";
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reg = <0x170 0x10>;
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axi_dev_1 {
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...
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};
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};
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