2019-07-16 20:17:13 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_PX30_COMMON_H
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#define __CONFIG_PX30_COMMON_H
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#include "rockchip-common.h"
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2023-01-09 10:36:41 +00:00
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#define CFG_IRAM_BASE 0xff0e0000
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2019-07-16 20:17:13 +00:00
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#define GICD_BASE 0xff131000
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#define GICC_BASE 0xff132000
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0
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2019-07-16 20:17:13 +00:00
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#define SDRAM_MAX_SIZE 0xff000000
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00500000\0" \
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"pxefile_addr_r=0x00600000\0" \
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"fdt_addr_r=0x08300000\0" \
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"kernel_addr_r=0x00280000\0" \
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"kernel_addr_c=0x03e80000\0" \
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"ramdisk_addr_r=0x0a200000\0"
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2022-12-04 15:03:50 +00:00
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#define CFG_EXTRA_ENV_SETTINGS \
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2019-07-16 20:17:13 +00:00
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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ROCKCHIP_DEVICE_SETTINGS \
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2023-04-24 01:49:51 +00:00
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"boot_targets=" BOOT_TARGETS "\0"
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2019-07-16 20:17:13 +00:00
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#endif
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