mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
597 lines
15 KiB
Text
597 lines
15 KiB
Text
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/*
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* Copyright 2018 Logic PD, Inc.
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* Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/ {
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keyboard {
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compatible = "gpio-keys";
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btn0 {
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gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
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label = "btn0";
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linux,code = <KEY_WAKEUP>;
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debounce-interval = <10>;
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wakeup-source;
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};
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btn1 {
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gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
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label = "btn1";
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linux,code = <KEY_WAKEUP>;
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debounce-interval = <10>;
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wakeup-source;
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};
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btn2 {
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gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
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label = "btn2";
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linux,code = <KEY_WAKEUP>;
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debounce-interval = <10>;
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wakeup-source;
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};
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btn3 {
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gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
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label = "btn3";
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linux,code = <KEY_WAKEUP>;
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debounce-interval = <10>;
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wakeup-source;
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};
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};
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leds {
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compatible = "gpio-leds";
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gen_led0 {
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label = "led0";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led0>;
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gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "cpu0";
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};
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gen_led1 {
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label = "led1";
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gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
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};
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gen_led2 {
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label = "led2";
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gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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gen_led3 {
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label = "led3";
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gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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};
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reg_usb_otg_vbus: regulator-otg-vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_h1_vbus: regulator-usbh1vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_3v3: regulator-3v3@2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_3v3>;
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compatible = "regulator-fixed";
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regulator-name = "reg_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_enet: regulator-ethernet@3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_pwr>;
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compatible = "regulator-fixed";
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regulator-name = "ethernet-supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <70000>;
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enable-active-high;
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vin-supply = <&sw4_reg>;
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};
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reg_audio: regulator-audio@4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_audio>;
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compatible = "regulator-fixed";
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regulator-name = "3v3_aud";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_3v3>;
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};
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reg_hdmi: regulator-hdmi@5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_hdmi>;
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compatible = "regulator-fixed";
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regulator-name = "hdmi-supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <®_3v3>;
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};
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reg_uart3: regulator-uart3@6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_uart3>;
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compatible = "regulator-fixed";
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regulator-name = "uart3-supply";
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gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_3v3>;
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};
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reg_1v8: regulator-1v8@7 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_1v8>;
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compatible = "regulator-fixed";
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regulator-name = "1v8-supply";
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gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_3v3>;
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};
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reg_pcie: regulator@8 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie_reg>;
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regulator-name = "MPCIE_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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mipi_pwr: regulator@9 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mipi_pwr>;
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regulator-name = "mipi_pwr_en";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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sound {
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compatible = "fsl,imx-audio-wm8962";
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model = "wm8962-audio";
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ssi-controller = <&ssi2>;
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audio-codec = <&codec>;
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audio-routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"Ext Spk", "SPKOUTL",
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"Ext Spk", "SPKOUTR",
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"AMIC", "MICBIAS",
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"IN3R", "AMIC";
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mux-int-port = <2>;
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mux-ext-port = <4>;
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};
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "okay";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "disabled";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usbh1 {
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vbus-supply = <®_usb_h1_vbus>;
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status = "okay";
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};
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&usbotg {
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vbus-supply = <®_usb_otg_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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disable-over-current;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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phy-reset-duration = <10>;
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phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
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phy-supply = <®_enet>;
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interrupt-parent = <&gpio1>;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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no-1-8-v;
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keep-power-in-suspend;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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status = "okay";
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codec: wm8962@1a {
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compatible = "wlf,wm8962";
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reg = <0x1a>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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clock-names = "xclk";
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DCVDD-supply = <®_audio>;
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DBVDD-supply = <®_audio>;
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AVDD-supply = <®_audio>;
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CPVDD-supply = <®_audio>;
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MICVDD-supply = <®_audio>;
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PLLVDD-supply = <®_audio>;
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SPKVDD1-supply = <®_audio>;
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SPKVDD2-supply = <®_audio>;
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gpio-cfg = <
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0x0000 /* 0:Default */
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0x0000 /* 1:Default */
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0x0013 /* 2:FN_DMICCLK */
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0x0000 /* 3:Default */
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0x8014 /* 4:FN_DMICCDAT */
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0x0000 /* 5:Default */
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>;
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};
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};
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&i2c3 {
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ov5640: camera@10 {
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compatible = "ovti,ov5640";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ov5640>;
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reg = <0x10>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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clock-names = "xclk";
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DOVDD-supply = <&mipi_pwr>;
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AVDD-supply = <&mipi_pwr>;
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DVDD-supply = <&mipi_pwr>;
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reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
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powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
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port {
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ov5640_to_mipi_csi2: endpoint {
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remote-endpoint = <&mipi_csi2_in>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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};
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pcf8575: gpio@20 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcf8574>;
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compatible = "nxp,pcf8575";
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reg = <0x20>;
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interrupt-parent = <&gpio6>;
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interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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lines-initial-states = <0x0710>;
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wakeup-source;
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};
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};
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&mipi_csi {
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status = "okay";
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port@0 {
|
||
|
|
reg = <0>;
|
||
|
|
|
||
|
|
mipi_csi2_in: endpoint {
|
||
|
|
remote-endpoint = <&ov5640_to_mipi_csi2>;
|
||
|
|
clock-lanes = <0>;
|
||
|
|
data-lanes = <1 2>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pcie {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
||
|
|
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||
|
|
status = "okay";
|
||
|
|
vpcie-supply = <®_pcie>;
|
||
|
|
/* fsl,max-link-speed = <2>; */
|
||
|
|
};
|
||
|
|
|
||
|
|
&ssi2 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc {
|
||
|
|
|
||
|
|
pinctrl_audmux: audmuxgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
|
||
|
|
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
|
||
|
|
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
|
||
|
|
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1 {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_enet_pwr: enet_pwr {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_mipi_pwr: pwr_mipi {
|
||
|
|
fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ov5640: ov5640grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1
|
||
|
|
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_hdmi: reg_hdmi {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3: uart3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
|
||
|
|
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg: usbotggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
|
||
|
|
MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ecspi1: ecspi1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
||
|
|
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
||
|
|
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
||
|
|
MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_enet: enetgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
|
||
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||
|
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
|
||
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
|
||
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
|
||
|
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
|
||
|
|
MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_audio: audio-reg {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pcie: pcie {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
|
||
|
|
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pcie_reg: pciereggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pcf8574: pcf8575-pins {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_lcd: lcdgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
|
||
|
|
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
|
||
|
|
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
|
||
|
|
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
|
||
|
|
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
|
||
|
|
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||
|
|
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm3: pwm3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_uart3: uart3reg {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_3v3: reg-3v3 {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_1v8: reg-1v8 {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_led0: led0 {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|