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u-boot/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0 */
arm: socfpga: Add system manager for Arria 10 Add system manager register struct and macros for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:40 +00:00
/*
arm: socfpga: arria10: Setting image magic value to romcode initswstate reg The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-11-07 15:08:54 +00:00
* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
arm: socfpga: Add system manager for Arria 10 Add system manager register struct and macros for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:40 +00:00
*/
#ifndef _SYSTEM_MANAGER_ARRIA10_H_
#define _SYSTEM_MANAGER_ARRIA10_H_
arm: socfpga: Convert system manager from struct to defines Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-08 02:38:20 +00:00
#define SYSMGR_A10_WDDBG 0x08
#define SYSMGR_A10_BOOTINFO 0x0c
#define SYSMGR_A10_DMA 0x20
#define SYSMGR_A10_DMA_PERIPH 0x24
#define SYSMGR_A10_SDMMC 0x28
#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
#define SYSMGR_A10_EMAC_GLOBAL 0x40
#define SYSMGR_A10_EMAC0 0x44
#define SYSMGR_A10_EMAC1 0x48
#define SYSMGR_A10_EMAC2 0x4c
#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
#define SYSMGR_A10_FPGAINTF_EN0 0x64
#define SYSMGR_A10_FPGAINTF_EN1 0x68
#define SYSMGR_A10_FPGAINTF_EN2 0x6c
#define SYSMGR_A10_FPGAINTF_EN3 0x70
#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
#define SYSMGR_A10_ECC_INTMASK_SET 0x94
#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
#define SYSMGR_A10_NOC_TIMEOUT 0xc0
#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
#define SYSMGR_A10_NOC_IDLEACK 0xd0
#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-11-07 15:08:55 +00:00
#define SYSMGR_A10_ROMCODE_CTRL 0x204
arm: socfpga: arria10: Setting image magic value to romcode initswstate reg The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-11-07 15:08:54 +00:00
#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-11-07 15:08:55 +00:00
#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
#define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
#define SYSMGR_A10_ISW_HANDOFF_7 0x1c
arm: socfpga: Convert system manager from struct to defines Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-08 02:38:20 +00:00
#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
arm: socfpga: Add system manager for Arria 10 Add system manager register struct and macros for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:40 +00:00
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */
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