mirror of
https://github.com/AsahiLinux/u-boot
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548 lines
13 KiB
C
548 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Macronix International Co., Ltd.
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*
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* Authors:
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* zhengxunli <zhengxunli@mxic.com.tw>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <linux/bug.h>
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#include <linux/iopoll.h>
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#define HC_CFG 0x0
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#define HC_CFG_IF_CFG(x) ((x) << 27)
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#define HC_CFG_DUAL_SLAVE BIT(31)
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#define HC_CFG_INDIVIDUAL BIT(30)
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#define HC_CFG_NIO(x) (((x) / 4) << 27)
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#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
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#define HC_CFG_TYPE_SPI_NOR 0
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#define HC_CFG_TYPE_SPI_NAND 1
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#define HC_CFG_TYPE_SPI_RAM 2
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#define HC_CFG_TYPE_RAW_NAND 3
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#define HC_CFG_SLV_ACT(x) ((x) << 21)
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#define HC_CFG_CLK_PH_EN BIT(20)
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#define HC_CFG_CLK_POL_INV BIT(19)
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#define HC_CFG_BIG_ENDIAN BIT(18)
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#define HC_CFG_DATA_PASS BIT(17)
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#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
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#define HC_CFG_MAN_START_EN BIT(3)
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#define HC_CFG_MAN_START BIT(2)
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#define HC_CFG_MAN_CS_EN BIT(1)
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#define HC_CFG_MAN_CS_ASSERT BIT(0)
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#define INT_STS 0x4
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#define INT_STS_EN 0x8
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#define INT_SIG_EN 0xc
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#define INT_STS_ALL GENMASK(31, 0)
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#define INT_RDY_PIN BIT(26)
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#define INT_RDY_SR BIT(25)
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#define INT_LNR_SUSP BIT(24)
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#define INT_ECC_ERR BIT(17)
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#define INT_CRC_ERR BIT(16)
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#define INT_LWR_DIS BIT(12)
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#define INT_LRD_DIS BIT(11)
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#define INT_SDMA_INT BIT(10)
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#define INT_DMA_FINISH BIT(9)
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#define INT_RX_NOT_FULL BIT(3)
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#define INT_RX_NOT_EMPTY BIT(2)
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#define INT_TX_NOT_FULL BIT(1)
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#define INT_TX_EMPTY BIT(0)
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#define HC_EN 0x10
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#define HC_EN_BIT BIT(0)
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#define TXD(x) (0x14 + ((x) * 4))
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#define RXD 0x24
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#define SS_CTRL(s) (0x30 + ((s) * 4))
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#define LRD_CFG 0x44
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#define LWR_CFG 0x80
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#define RWW_CFG 0x70
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#define OP_READ BIT(23)
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#define OP_DUMMY_CYC(x) ((x) << 17)
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#define OP_ADDR_BYTES(x) ((x) << 14)
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#define OP_CMD_BYTES(x) (((x) - 1) << 13)
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#define OP_OCTA_CRC_EN BIT(12)
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#define OP_DQS_EN BIT(11)
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#define OP_ENHC_EN BIT(10)
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#define OP_PREAMBLE_EN BIT(9)
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#define OP_DATA_DDR BIT(8)
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#define OP_DATA_BUSW(x) ((x) << 6)
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#define OP_ADDR_DDR BIT(5)
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#define OP_ADDR_BUSW(x) ((x) << 3)
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#define OP_CMD_DDR BIT(2)
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#define OP_CMD_BUSW(x) (x)
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#define OP_BUSW_1 0
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#define OP_BUSW_2 1
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#define OP_BUSW_4 2
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#define OP_BUSW_8 3
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#define OCTA_CRC 0x38
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#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
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#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
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#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
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#define ONFI_DIN_CNT(s) (0x3c + (s))
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#define LRD_CTRL 0x48
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#define RWW_CTRL 0x74
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#define LWR_CTRL 0x84
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#define LMODE_EN BIT(31)
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#define LMODE_SLV_ACT(x) ((x) << 21)
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#define LMODE_CMD1(x) ((x) << 8)
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#define LMODE_CMD0(x) (x)
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#define LRD_ADDR 0x4c
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#define LWR_ADDR 0x88
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#define LRD_RANGE 0x50
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#define LWR_RANGE 0x8c
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#define AXI_SLV_ADDR 0x54
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#define DMAC_RD_CFG 0x58
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#define DMAC_WR_CFG 0x94
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#define DMAC_CFG_PERIPH_EN BIT(31)
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#define DMAC_CFG_ALLFLUSH_EN BIT(30)
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#define DMAC_CFG_LASTFLUSH_EN BIT(29)
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#define DMAC_CFG_QE(x) (((x) + 1) << 16)
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#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
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#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
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#define DMAC_CFG_DIR_READ BIT(1)
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#define DMAC_CFG_START BIT(0)
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#define DMAC_RD_CNT 0x5c
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#define DMAC_WR_CNT 0x98
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#define SDMA_ADDR 0x60
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#define DMAM_CFG 0x64
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#define DMAM_CFG_START BIT(31)
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#define DMAM_CFG_CONT BIT(30)
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#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
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#define DMAM_CFG_DIR_READ BIT(1)
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#define DMAM_CFG_EN BIT(0)
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#define DMAM_CNT 0x68
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#define LNR_TIMER_TH 0x6c
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#define RDM_CFG0 0x78
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#define RDM_CFG0_POLY(x) (x)
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#define RDM_CFG1 0x7c
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#define RDM_CFG1_RDM_EN BIT(31)
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#define RDM_CFG1_SEED(x) (x)
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#define LWR_SUSP_CTRL 0x90
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#define LWR_SUSP_CTRL_EN BIT(31)
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#define DMAS_CTRL 0x9c
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#define DMAS_CTRL_EN BIT(31)
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#define DMAS_CTRL_DIR_READ BIT(30)
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#define DATA_STROB 0xa0
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#define DATA_STROB_EDO_EN BIT(2)
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#define DATA_STROB_INV_POL BIT(1)
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#define DATA_STROB_DELAY_2CYC BIT(0)
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#define IDLY_CODE(x) (0xa4 + ((x) * 4))
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#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
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#define GPIO 0xc4
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#define GPIO_PT(x) BIT(3 + ((x) * 16))
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#define GPIO_RESET(x) BIT(2 + ((x) * 16))
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#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
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#define GPIO_WPB(x) BIT((x) * 16)
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#define HC_VER 0xd0
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#define HW_TEST(x) (0xe0 + ((x) * 4))
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struct mxic_spi_priv {
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struct clk *send_clk;
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struct clk *send_dly_clk;
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void __iomem *regs;
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u32 cur_speed_hz;
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};
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static int mxic_spi_clk_enable(struct mxic_spi_priv *priv)
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{
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int ret;
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ret = clk_prepare_enable(priv->send_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->send_dly_clk);
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if (ret)
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goto err_send_dly_clk;
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return ret;
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err_send_dly_clk:
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clk_disable_unprepare(priv->send_clk);
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return ret;
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}
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static void mxic_spi_clk_disable(struct mxic_spi_priv *priv)
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{
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clk_disable_unprepare(priv->send_clk);
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clk_disable_unprepare(priv->send_dly_clk);
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}
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static void mxic_spi_set_input_delay_dqs(struct mxic_spi_priv *priv,
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u8 idly_code)
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{
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writel(IDLY_CODE_VAL(0, idly_code) |
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IDLY_CODE_VAL(1, idly_code) |
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IDLY_CODE_VAL(2, idly_code) |
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IDLY_CODE_VAL(3, idly_code),
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priv->regs + IDLY_CODE(0));
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writel(IDLY_CODE_VAL(4, idly_code) |
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IDLY_CODE_VAL(5, idly_code) |
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IDLY_CODE_VAL(6, idly_code) |
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IDLY_CODE_VAL(7, idly_code),
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priv->regs + IDLY_CODE(1));
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}
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static int mxic_spi_clk_setup(struct mxic_spi_priv *priv, uint freq)
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{
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int ret;
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ret = clk_set_rate(priv->send_clk, freq);
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if (ret)
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return ret;
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ret = clk_set_rate(priv->send_dly_clk, freq);
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if (ret)
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return ret;
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/*
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* A constant delay range from 0x0 ~ 0x1F for input delay,
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* the unit is 78 ps, the max input delay is 2.418 ns.
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*/
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mxic_spi_set_input_delay_dqs(priv, 0xf);
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return 0;
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}
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static int mxic_spi_set_speed(struct udevice *bus, uint freq)
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{
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struct mxic_spi_priv *priv = dev_get_priv(bus);
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int ret;
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if (priv->cur_speed_hz == freq)
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return 0;
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mxic_spi_clk_disable(priv);
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ret = mxic_spi_clk_setup(priv, freq);
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if (ret)
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return ret;
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ret = mxic_spi_clk_enable(priv);
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if (ret)
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return ret;
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priv->cur_speed_hz = freq;
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return 0;
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}
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static int mxic_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct mxic_spi_priv *priv = dev_get_priv(bus);
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u32 hc_config = 0;
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if (mode & SPI_CPHA)
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hc_config |= HC_CFG_CLK_PH_EN;
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if (mode & SPI_CPOL)
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hc_config |= HC_CFG_CLK_POL_INV;
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writel(hc_config, priv->regs + HC_CFG);
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return 0;
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}
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static void mxic_spi_hw_init(struct mxic_spi_priv *priv)
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{
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writel(0, priv->regs + DATA_STROB);
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writel(INT_STS_ALL, priv->regs + INT_STS_EN);
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writel(0, priv->regs + HC_EN);
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writel(0, priv->regs + LRD_CFG);
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writel(0, priv->regs + LRD_CTRL);
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writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
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HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
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priv->regs + HC_CFG);
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}
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static int mxic_spi_data_xfer(struct mxic_spi_priv *priv, const void *txbuf,
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void *rxbuf, unsigned int len)
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{
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unsigned int pos = 0;
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while (pos < len) {
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unsigned int nbytes = len - pos;
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u32 data = 0xffffffff;
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u32 sts;
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int ret;
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if (nbytes > 4)
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nbytes = 4;
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if (txbuf)
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memcpy(&data, txbuf + pos, nbytes);
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ret = readl_poll_timeout(priv->regs + INT_STS, sts,
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sts & INT_TX_EMPTY, 1000000);
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if (ret)
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return ret;
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writel(data, priv->regs + TXD(nbytes % 4));
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if (rxbuf) {
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ret = readl_poll_timeout(priv->regs + INT_STS, sts,
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sts & INT_TX_EMPTY,
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1000000);
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if (ret)
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return ret;
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ret = readl_poll_timeout(priv->regs + INT_STS, sts,
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sts & INT_RX_NOT_EMPTY,
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1000000);
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if (ret)
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return ret;
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data = readl(priv->regs + RXD);
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data >>= (8 * (4 - nbytes));
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memcpy(rxbuf + pos, &data, nbytes);
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WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY);
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} else {
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readl(priv->regs + RXD);
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}
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WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY);
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pos += nbytes;
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}
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return 0;
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}
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static bool mxic_spi_mem_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
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op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
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return false;
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if (op->addr.nbytes > 7)
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return false;
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return spi_mem_default_supports_op(slave, op);
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}
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static int mxic_spi_mem_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
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struct udevice *bus = slave->dev->parent;
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struct mxic_spi_priv *priv = dev_get_priv(bus);
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int nio = 1, i, ret;
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u32 ss_ctrl;
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u8 addr[8], dummy_bytes = 0;
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if (slave->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
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nio = 8;
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else if (slave->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
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nio = 4;
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else if (slave->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
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nio = 2;
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writel(HC_CFG_NIO(nio) |
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HC_CFG_TYPE(slave_plat->cs, HC_CFG_TYPE_SPI_NOR) |
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HC_CFG_SLV_ACT(slave_plat->cs) | HC_CFG_IDLE_SIO_LVL(1) |
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HC_CFG_MAN_CS_EN,
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priv->regs + HC_CFG);
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writel(HC_EN_BIT, priv->regs + HC_EN);
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ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
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if (op->addr.nbytes)
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ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
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OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
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/*
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* Since the SPI MXIC dummy buswidth is aligned with the data buswidth,
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* the dummy byte needs to be recalculated to send out the correct
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* dummy cycle.
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*/
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if (op->dummy.nbytes) {
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dummy_bytes = op->dummy.nbytes /
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op->addr.buswidth *
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op->data.buswidth;
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ss_ctrl |= OP_DUMMY_CYC(dummy_bytes);
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}
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if (op->data.nbytes) {
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ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
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if (op->data.dir == SPI_MEM_DATA_IN)
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ss_ctrl |= OP_READ;
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}
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writel(ss_ctrl, priv->regs + SS_CTRL(slave_plat->cs));
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writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
|
||
|
priv->regs + HC_CFG);
|
||
|
|
||
|
ret = mxic_spi_data_xfer(priv, &op->cmd.opcode, NULL, 1);
|
||
|
if (ret)
|
||
|
goto out;
|
||
|
|
||
|
for (i = 0; i < op->addr.nbytes; i++)
|
||
|
addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
|
||
|
|
||
|
ret = mxic_spi_data_xfer(priv, addr, NULL, op->addr.nbytes);
|
||
|
if (ret)
|
||
|
goto out;
|
||
|
|
||
|
ret = mxic_spi_data_xfer(priv, NULL, NULL, dummy_bytes);
|
||
|
if (ret)
|
||
|
goto out;
|
||
|
|
||
|
ret = mxic_spi_data_xfer(priv,
|
||
|
op->data.dir == SPI_MEM_DATA_OUT ?
|
||
|
op->data.buf.out : NULL,
|
||
|
op->data.dir == SPI_MEM_DATA_IN ?
|
||
|
op->data.buf.in : NULL,
|
||
|
op->data.nbytes);
|
||
|
|
||
|
out:
|
||
|
writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
|
||
|
priv->regs + HC_CFG);
|
||
|
writel(0, priv->regs + HC_EN);
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
|
||
|
.supports_op = mxic_spi_mem_supports_op,
|
||
|
.exec_op = mxic_spi_mem_exec_op,
|
||
|
};
|
||
|
|
||
|
static int mxic_spi_claim_bus(struct udevice *dev)
|
||
|
{
|
||
|
struct udevice *bus = dev_get_parent(dev);
|
||
|
struct mxic_spi_priv *priv = dev_get_priv(bus);
|
||
|
|
||
|
writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
|
||
|
priv->regs + HC_CFG);
|
||
|
writel(HC_EN_BIT, priv->regs + HC_EN);
|
||
|
writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
|
||
|
priv->regs + HC_CFG);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int mxic_spi_release_bus(struct udevice *dev)
|
||
|
{
|
||
|
struct udevice *bus = dev_get_parent(dev);
|
||
|
struct mxic_spi_priv *priv = dev_get_priv(bus);
|
||
|
|
||
|
writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
|
||
|
priv->regs + HC_CFG);
|
||
|
writel(0, priv->regs + HC_EN);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int mxic_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||
|
const void *dout, void *din, unsigned long flags)
|
||
|
{
|
||
|
struct udevice *bus = dev_get_parent(dev);
|
||
|
struct mxic_spi_priv *priv = dev_get_priv(bus);
|
||
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
||
|
unsigned int busw = OP_BUSW_1;
|
||
|
unsigned int len = bitlen / 8;
|
||
|
int ret;
|
||
|
|
||
|
if (dout && din) {
|
||
|
if (((slave->mode & SPI_TX_QUAD) &&
|
||
|
!(slave->mode & SPI_RX_QUAD)) ||
|
||
|
((slave->mode & SPI_TX_DUAL) &&
|
||
|
!(slave->mode & SPI_RX_DUAL)))
|
||
|
return -ENOTSUPP;
|
||
|
}
|
||
|
|
||
|
if (din) {
|
||
|
if (slave->mode & SPI_TX_QUAD)
|
||
|
busw = OP_BUSW_4;
|
||
|
else if (slave->mode & SPI_TX_DUAL)
|
||
|
busw = OP_BUSW_2;
|
||
|
} else if (dout) {
|
||
|
if (slave->mode & SPI_RX_QUAD)
|
||
|
busw = OP_BUSW_4;
|
||
|
else if (slave->mode & SPI_RX_DUAL)
|
||
|
busw = OP_BUSW_2;
|
||
|
}
|
||
|
|
||
|
writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
|
||
|
OP_DATA_BUSW(busw) | (din ? OP_READ : 0),
|
||
|
priv->regs + SS_CTRL(0));
|
||
|
|
||
|
ret = mxic_spi_data_xfer(priv, dout, din, len);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int mxic_spi_probe(struct udevice *bus)
|
||
|
{
|
||
|
struct mxic_spi_priv *priv = dev_get_priv(bus);
|
||
|
|
||
|
priv->regs = (void *)dev_read_addr(bus);
|
||
|
|
||
|
priv->send_clk = devm_clk_get(bus, "send_clk");
|
||
|
if (IS_ERR(priv->send_clk))
|
||
|
return PTR_ERR(priv->send_clk);
|
||
|
|
||
|
priv->send_dly_clk = devm_clk_get(bus, "send_dly_clk");
|
||
|
if (IS_ERR(priv->send_dly_clk))
|
||
|
return PTR_ERR(priv->send_dly_clk);
|
||
|
|
||
|
mxic_spi_hw_init(priv);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static const struct dm_spi_ops mxic_spi_ops = {
|
||
|
.claim_bus = mxic_spi_claim_bus,
|
||
|
.release_bus = mxic_spi_release_bus,
|
||
|
.xfer = mxic_spi_xfer,
|
||
|
.set_speed = mxic_spi_set_speed,
|
||
|
.set_mode = mxic_spi_set_mode,
|
||
|
.mem_ops = &mxic_spi_mem_ops,
|
||
|
};
|
||
|
|
||
|
static const struct udevice_id mxic_spi_ids[] = {
|
||
|
{ .compatible = "mxicy,mx25f0a-spi", },
|
||
|
{ }
|
||
|
};
|
||
|
|
||
|
U_BOOT_DRIVER(mxic_spi) = {
|
||
|
.name = "mxic_spi",
|
||
|
.id = UCLASS_SPI,
|
||
|
.of_match = mxic_spi_ids,
|
||
|
.ops = &mxic_spi_ops,
|
||
|
.priv_auto = sizeof(struct mxic_spi_priv),
|
||
|
.probe = mxic_spi_probe,
|
||
|
};
|