2020-01-09 08:52:17 +00:00
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* (C) Copyright 2019 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#ifndef _ROCKCHIP_CLOCK_H
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#define _ROCKCHIP_CLOCK_H
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#if defined(CONFIG_ROCKCHIP_RK3288)
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# include <asm/arch-rockchip/cru_rk3288.h>
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#elif defined(CONFIG_ROCKCHIP_RK3399)
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# include <asm/arch-rockchip/cru_rk3399.h>
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#endif
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2020-01-09 08:52:18 +00:00
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/* CRU_GLB_RST_ST */
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enum {
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GLB_POR_RST,
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FST_GLB_RST_ST = BIT(0),
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SND_GLB_RST_ST = BIT(1),
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FST_GLB_TSADC_RST_ST = BIT(2),
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SND_GLB_TSADC_RST_ST = BIT(3),
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FST_GLB_WDT_RST_ST = BIT(4),
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SND_GLB_WDT_RST_ST = BIT(5),
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GLB_RST_ST_MASK = GENMASK(5, 0),
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};
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2020-01-09 08:52:17 +00:00
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#define MHz 1000000
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#endif /* _ROCKCHIP_CLOCK_H */
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