2022-08-25 08:11:18 +00:00
|
|
|
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
2021-05-27 13:52:11 +00:00
|
|
|
/*
|
2022-08-25 08:11:18 +00:00
|
|
|
* Copyright (C) 2019 SiFive, Inc.
|
2021-05-27 13:52:11 +00:00
|
|
|
* Wesley Terpstra
|
|
|
|
* Paul Walmsley
|
|
|
|
* Zong Li
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
|
|
|
|
#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
|
|
|
|
|
|
|
|
/* Clock indexes for use by Device Tree data and the PRCI driver */
|
|
|
|
|
2022-08-25 08:11:18 +00:00
|
|
|
#define FU740_PRCI_CLK_COREPLL 0
|
|
|
|
#define FU740_PRCI_CLK_DDRPLL 1
|
|
|
|
#define FU740_PRCI_CLK_GEMGXLPLL 2
|
|
|
|
#define FU740_PRCI_CLK_DVFSCOREPLL 3
|
|
|
|
#define FU740_PRCI_CLK_HFPCLKPLL 4
|
|
|
|
#define FU740_PRCI_CLK_CLTXPLL 5
|
|
|
|
#define FU740_PRCI_CLK_TLCLK 6
|
|
|
|
#define FU740_PRCI_CLK_PCLK 7
|
|
|
|
#define FU740_PRCI_CLK_PCIE_AUX 8
|
2021-05-27 13:52:11 +00:00
|
|
|
|
2022-08-25 08:11:18 +00:00
|
|
|
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
|