mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-26 21:13:48 +00:00
455 lines
6.6 KiB
ArmAsm
455 lines
6.6 KiB
ArmAsm
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/* Memory sub-system initialization code */
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/au1x00.h>
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#include <asm/mipsregs.h>
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#define CP0_Config0 $16
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#define MEM_1MS ((CFG_MHZ) * 1000)
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#define GPIO_RJ1LY (1<<22)
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#define GPIO_CFRESET (1<<10)
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.text
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.set noreorder
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.set mips32
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Step 2) Establish Status Register
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* (set BEV, clear ERL, clear EXL, clear IE)
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*/
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li t1, 0x00400000
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mtc0 t1, CP0_STATUS
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/*
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* Step 3) Establish CP0 Config0
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* (set OD, set K0=3)
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*/
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li t1, 0x00080003
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mtc0 t1, CP0_CONFIG
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/*
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* Step 4) Disable Watchpoint facilities
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*/
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li t1, 0x00000000
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mtc0 t1, CP0_WATCHLO
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mtc0 t1, CP0_IWATCHLO
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/*
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* Step 5) Disable the performance counters
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*/
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mtc0 zero, CP0_PERFORMANCE
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nop
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/*
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* Step 6) Establish EJTAG Debug register
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*/
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mtc0 zero, CP0_DEBUG
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nop
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/*
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* Step 7) Establish Cause
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* (set IV bit)
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*/
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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/* Establish Wired (and Random) */
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mtc0 zero, CP0_WIRED
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nop
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/* No workaround if running from ram */
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lui t0, 0xffc0
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lui t3, 0xbfc0
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and t1, ra, t0
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bne t1, t3, noCacheJump
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nop
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/*** From AMD YAMON ***/
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/*
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* Step 8) Initialize the caches
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*/
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li t0, (16*1024)
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li t1, 32
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li t2, 0x80000000
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addu t3, t0, t2
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cacheloop:
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cache 0, 0(t2)
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cache 1, 0(t2)
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addu t2, t1
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bne t2, t3, cacheloop
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nop
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/* Save return address */
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move t3, ra
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/* Run from cacheable space now */
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bal cachehere
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nop
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cachehere:
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li t1, ~0x20000000 /* convert to KSEG0 */
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and t0, ra, t1
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addi t0, 5*4 /* 5 insns beyond cachehere */
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jr t0
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nop
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/* Restore return address */
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move ra, t3
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/*
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* Step 9) Initialize the TLB
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*/
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li t0, 0 # index value
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li t1, 0x00000000 # entryhi value
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li t2, 32 # 32 entries
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tlbloop:
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/* Probe TLB for matching EntryHi */
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mtc0 t1, CP0_ENTRYHI
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tlbp
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nop
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/* Examine Index[P], 1=no matching entry */
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mfc0 t3, CP0_INDEX
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li t4, 0x80000000
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and t3, t4, t3
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addiu t1, t1, 1 # increment t1 (asid)
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beq zero, t3, tlbloop
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nop
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/* Initialize the TLB entry */
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mtc0 t0, CP0_INDEX
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mtc0 zero, CP0_ENTRYLO0
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mtc0 zero, CP0_ENTRYLO1
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mtc0 zero, CP0_PAGEMASK
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tlbwi
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/* Do it again */
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addiu t0, t0, 1
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bne t0, t2, tlbloop
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nop
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/* First setup pll:s to make serial work ok */
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/* We have a 12.5 MHz crystal */
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li t0, SYS_CPUPLL
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li t1, 0x28 /* CPU clock, 500 MHz */
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sw t1, 0(t0)
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sync
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nop
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nop
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/* wait 1mS for clocks to settle */
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li t1, MEM_1MS
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1: add t1, -1
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bne t1, zero, 1b
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nop
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/* Setup AUX PLL */
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li t0, SYS_AUXPLL
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li t1, 0
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sw t1, 0(t0) /* aux pll */
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sync
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/* Static memory controller */
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/* RCE0 - can not change while fetching, do so from icache */
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move t2, ra /* Store return address */
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bal getAddr
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nop
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getAddr:
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move t1, ra
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move ra, t2 /* Move return addess back */
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cache 0x14,0(t1)
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cache 0x14,32(t1)
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/*** /From YAMON ***/
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noCacheJump:
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/* Static memory controller */
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/* RCE0 AMD 29LV800 Flash */
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li t0, MEM_STCFG0
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li t1, 0x00000243
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sw t1, 0(t0)
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li t0, MEM_STTIME0
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li t1, 0x040181D7 /* FIXME */
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sw t1, 0(t0)
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li t0, MEM_STADDR0
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li t1, 0x11E03F80
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sw t1, 0(t0)
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/* RCE1 PCMCIA 250ns */
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li t0, MEM_STCFG1
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li t1, 0x00000002
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sw t1, 0(t0)
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li t0, MEM_STTIME1
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li t1, 0x280E3E07
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sw t1, 0(t0)
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li t0, MEM_STADDR1
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li t1, 0x10000000
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sw t1, 0(t0)
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/* RCE2 CP Altera */
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li t0, MEM_STCFG2
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li t1, 0x00000280 /* BE, EW */
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sw t1, 0(t0)
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li t0, MEM_STTIME2
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li t1, 0x0303000c
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sw t1, 0(t0)
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li t0, MEM_STADDR2
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li t1, 0x10c03f80 /* 1 MB */
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sw t1, 0(t0)
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/* RCE3 DP Altera */
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li t0, MEM_STCFG3
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li t1, 0x00000280 /* BE, EW */
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sw t1, 0(t0)
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li t0, MEM_STTIME3
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li t1, 0x0303000c
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sw t1, 0(t0)
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li t0, MEM_STADDR3
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li t1, 0x10e03f80 /* 1 MB */
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sw t1, 0(t0)
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sync
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/* Set peripherals to a known state */
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li t0, IC0_CFG0CLR
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li t1, 0xFFFFFFFF
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sw t1, 0(t0)
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li t0, IC0_CFG0CLR
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sw t1, 0(t0)
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li t0, IC0_CFG1CLR
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sw t1, 0(t0)
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li t0, IC0_CFG2CLR
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sw t1, 0(t0)
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li t0, IC0_SRCSET
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sw t1, 0(t0)
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li t0, IC0_ASSIGNSET
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sw t1, 0(t0)
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li t0, IC0_WAKECLR
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sw t1, 0(t0)
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li t0, IC0_RISINGCLR
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sw t1, 0(t0)
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li t0, IC0_FALLINGCLR
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sw t1, 0(t0)
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li t0, IC0_TESTBIT
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, IC1_CFG0CLR
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li t1, 0xFFFFFFFF
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sw t1, 0(t0)
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li t0, IC1_CFG0CLR
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sw t1, 0(t0)
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li t0, IC1_CFG1CLR
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sw t1, 0(t0)
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li t0, IC1_CFG2CLR
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sw t1, 0(t0)
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li t0, IC1_SRCSET
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sw t1, 0(t0)
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li t0, IC1_ASSIGNSET
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sw t1, 0(t0)
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li t0, IC1_WAKECLR
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sw t1, 0(t0)
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li t0, IC1_RISINGCLR
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sw t1, 0(t0)
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li t0, IC1_FALLINGCLR
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sw t1, 0(t0)
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li t0, IC1_TESTBIT
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, SYS_FREQCTRL0
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_FREQCTRL1
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_CLKSRC
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_PININPUTEN
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, 0xB1100100
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, 0xB1400100
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_WAKEMSK
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_WAKESRC
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li t1, 0x00000000
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sw t1, 0(t0)
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/* wait 1mS before setup */
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li t1, MEM_1MS
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1: add t1, -1
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bne t1, zero, 1b
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nop
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/* SDCS 0 SDRAM */
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li t0, MEM_SDMODE0
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li t1, 0x592CD1
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sw t1, 0(t0)
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li t0, MEM_SDMODE1
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, MEM_SDMODE2
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li t1, 0x00000000
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sw t1, 0(t0)
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/* 64 MB SDRAM at addr 0 */
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li t0, MEM_SDADDR0
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li t1, 0x001003F0
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sw t1, 0(t0)
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li t0, MEM_SDADDR1
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, MEM_SDADDR2
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, MEM_SDREFCFG
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li t1, 0x880007A1 /* Disable */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDPRECMD
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sw zero, 0(t0)
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sync
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li t0, MEM_SDAUTOREF
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sw zero, 0(t0)
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sync
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sw zero, 0(t0)
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sync
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li t0, MEM_SDREFCFG
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li t1, 0x8A0007A1 /* Enable */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD0
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li t1, 0x00000023
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sw t1, 0(t0)
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sync
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/* wait 1mS after setup */
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li t1, MEM_1MS
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1: add t1, -1
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bne t1, zero, 1b
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nop
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/* Setup GPIO pins */
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li t0, SYS_PINFUNC
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li t1, 0x00007025 /* 0x8080 */
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sw t1, 0(t0)
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li t0, SYS_TRIOUTCLR
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li t1, 0xFFFFFFFF /* 0x1FFF */
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sw t1, 0(t0)
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/* Turn yellow front led on */
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/* Release reset on CF */
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li t0, SYS_OUTPUTCLR
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li t1, GPIO_RJ1LG
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sw t1, 0(t0)
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li t0, SYS_OUTPUTSET
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li t1, GPIO_RJ1LY|GPIO_CFRESET
|
||
|
|
sw t1, 0(t0)
|
||
|
|
sync
|
||
|
|
j clearmem
|
||
|
|
nop
|
||
|
|
|
||
|
|
.globl memtest
|
||
|
|
memtest:
|
||
|
|
/* Fill memory with address */
|
||
|
|
li t0, 0x80000000
|
||
|
|
li t1, 0xFFF000 /* 64 MB */
|
||
|
|
mt0: sw t0, 0(t0)
|
||
|
|
add t1, -1
|
||
|
|
add t0, 4
|
||
|
|
bne t1, zero, mt0
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
/* Verify addr */
|
||
|
|
li t0, 0x80000000
|
||
|
|
li t1, 0xFFF000 /* 64 MB */
|
||
|
|
mt1: lw t2, 0(t0)
|
||
|
|
bne t0, t2, memhang
|
||
|
|
add t1, -1
|
||
|
|
add t0, 4
|
||
|
|
bne t1, zero, mt1
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
.globl clearmem
|
||
|
|
clearmem:
|
||
|
|
/* Clear memory */
|
||
|
|
li t0, 0x80000000
|
||
|
|
li t1, 0xFFF000 /* 64 MB */
|
||
|
|
mtc: sw zero, 0(t0)
|
||
|
|
add t1, -1
|
||
|
|
add t0, 4
|
||
|
|
bne t1, zero, mtc
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
memtestend:
|
||
|
|
j ra
|
||
|
|
nop
|
||
|
|
|
||
|
|
memhang:
|
||
|
|
b memhang
|
||
|
|
nop
|