2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2016-05-23 09:12:05 +00:00
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/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*/
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#ifndef _COMPHY_HPIPE_H_
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#define _COMPHY_HPIPE_H_
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2021-03-23 10:57:57 +00:00
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#define MAX_NUM_OF_FFE 8
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#define RX_TRAINING_TIMEOUT 500
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2016-05-23 09:12:05 +00:00
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/* SerDes IP register */
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#define SD_EXTERNAL_CONFIG0_REG 0
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#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
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#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
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(1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
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#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
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#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
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(0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
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#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
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#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
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(0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
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#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
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#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
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(1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
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#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
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#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
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(1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
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#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
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#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
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(1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
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#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
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#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
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(0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
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#define SD_EXTERNAL_CONFIG1_REG 0x4
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#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
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#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
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(0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
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#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
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#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
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(0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
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#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
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#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
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(0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
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#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
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#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
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(0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
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#define SD_EXTERNAL_CONFIG2_REG 0x8
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#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
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#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
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(0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
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#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
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(0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
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2016-05-23 09:12:05 +00:00
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2021-03-23 10:57:57 +00:00
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#define SD_EXTERNAL_STATUS_REG 0xc
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#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7
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#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \
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(1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define SD_EXTERNAL_STATUS0_REG 0x18
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#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
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#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
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(0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
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#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
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#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
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(0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
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#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
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#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
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(0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
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#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
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#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
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(0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
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2021-03-23 10:57:57 +00:00
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#define SD_EXTERNAL_STATUS1_REG 0x1c
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#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET 0
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#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK \
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(1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET)
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#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET 1
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#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK \
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(1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET)
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2016-05-23 09:12:05 +00:00
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/* HPIPE register */
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#define HPIPE_PWR_PLL_REG 0x4
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#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
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#define HPIPE_PWR_PLL_REF_FREQ_MASK \
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(0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
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#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
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#define HPIPE_PWR_PLL_PHY_MODE_MASK \
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(0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
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#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
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#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
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#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
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(0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
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2016-08-30 14:48:20 +00:00
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#define HPIPE_CAL_REG1_REG 0xc
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#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
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#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
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(0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
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#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
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#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
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(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
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2021-03-23 10:57:57 +00:00
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#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18
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#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8
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#define HPIPE_SQUELCH_THRESH_IN_MASK \
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(0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET)
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#define HPIPE_SQUELCH_DETECTED_OFFSET 14
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#define HPIPE_SQUELCH_DETECTED_MASK \
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(0x1 << HPIPE_SQUELCH_DETECTED_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_DFE_REG0 0x01C
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#define HPIPE_DFE_RES_FORCE_OFFSET 15
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#define HPIPE_DFE_RES_FORCE_MASK \
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(0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
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#define HPIPE_DFE_F3_F5_REG 0x028
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#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
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#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
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(0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
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#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
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#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
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(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
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#define HPIPE_G1_SET_0_REG 0x034
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2016-08-30 14:48:20 +00:00
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#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
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#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
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(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
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#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
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(0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
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(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
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(0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_G1_SET_1_REG 0x038
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#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
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#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
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(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
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#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
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#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
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(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
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#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
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(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
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#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
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#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
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(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
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#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
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(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
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#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
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(0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
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#define HPIPE_G2_SET_0_REG 0x3c
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#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
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#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
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(0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
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#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
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#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
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(0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
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(0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
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(0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
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#define HPIPE_G2_SET_1_REG 0x040
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#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
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#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
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(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
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#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
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#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
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(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
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#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
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#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
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(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
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#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
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#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
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(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
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#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
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#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
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(0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
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#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
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#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
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(0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
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#define HPIPE_G3_SET_0_REG 0x44
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#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
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#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
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(0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
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#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
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#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
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(0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
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#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
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#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
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(0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
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#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
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#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
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(0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
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#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
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#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
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(0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
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#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
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#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
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(0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
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#define HPIPE_G3_SET_1_REG 0x048
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#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
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#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
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(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
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#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
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#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
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(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
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#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
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#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
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(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
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#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
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#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
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(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
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#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
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#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
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(0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
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#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
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#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
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(0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
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#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
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#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
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(0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
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2016-05-23 09:12:05 +00:00
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2021-03-23 10:57:57 +00:00
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#define HPIPE_PHY_TEST_CONTROL_REG 0x54
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#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4
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#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \
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(0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET)
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#define HPIPE_PHY_TEST_RESET_OFFSET 14
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#define HPIPE_PHY_TEST_RESET_MASK \
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(0x1 << HPIPE_PHY_TEST_RESET_OFFSET)
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#define HPIPE_PHY_TEST_EN_OFFSET 15
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#define HPIPE_PHY_TEST_EN_MASK \
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(0x1 << HPIPE_PHY_TEST_EN_OFFSET)
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#define HPIPE_PHY_TEST_DATA_REG 0x6c
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#define HPIPE_PHY_TEST_DATA_OFFSET 0
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#define HPIPE_PHY_TEST_DATA_MASK \
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(0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_LOOPBACK_REG 0x08c
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#define HPIPE_LOOPBACK_SEL_OFFSET 1
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#define HPIPE_LOOPBACK_SEL_MASK \
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(0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
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2021-03-23 10:57:57 +00:00
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#define HPIPE_CDR_LOCK_OFFSET 7
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#define HPIPE_CDR_LOCK_MASK \
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(0x1 << HPIPE_CDR_LOCK_OFFSET)
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#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8
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#define HPIPE_CDR_LOCK_DET_EN_MASK \
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(0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_SYNC_PATTERN_REG 0x090
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2018-09-06 09:37:48 +00:00
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#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
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#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
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(0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
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#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
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#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
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(0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_INTERFACE_REG 0x94
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#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
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#define HPIPE_INTERFACE_GEN_MAX_MASK \
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(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
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2017-04-24 15:45:33 +00:00
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#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
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#define HPIPE_INTERFACE_DET_BYPASS_MASK \
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(0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
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#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
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(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
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#define HPIPE_ISOLATE_MODE_REG 0x98
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#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
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#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
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(0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
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#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
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#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
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(0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
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2016-08-30 14:48:20 +00:00
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#define HPIPE_G1_SET_2_REG 0xf4
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#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
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#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
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(0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
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#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
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#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
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(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
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|
2016-05-23 09:12:05 +00:00
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#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
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|
2017-04-24 15:45:26 +00:00
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#define HPIPE_VDD_CAL_CTRL_REG 0x114
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#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
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#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
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(0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
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2017-04-24 15:45:31 +00:00
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#define HPIPE_VDD_CAL_0_REG 0x108
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#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
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#define HPIPE_CAL_VDD_CONT_MODE_MASK \
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(0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_PCIE_REG0 0x120
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#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
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#define HPIPE_PCIE_IDLE_SYNC_MASK \
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(0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
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#define HPIPE_PCIE_SEL_BITS_OFFSET 13
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#define HPIPE_PCIE_SEL_BITS_MASK \
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(0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
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#define HPIPE_LANE_ALIGN_REG 0x124
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#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
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#define HPIPE_LANE_ALIGN_OFF_MASK \
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(0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
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#define HPIPE_MISC_REG 0x13C
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#define HPIPE_MISC_CLK100M_125M_OFFSET 4
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#define HPIPE_MISC_CLK100M_125M_MASK \
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(0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
|
2016-08-30 14:48:20 +00:00
|
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#define HPIPE_MISC_ICP_FORCE_OFFSET 5
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#define HPIPE_MISC_ICP_FORCE_MASK \
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(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
|
2016-05-23 09:12:05 +00:00
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#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
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#define HPIPE_MISC_TXDCLK_2X_MASK \
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(0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
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#define HPIPE_MISC_CLK500_EN_OFFSET 7
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#define HPIPE_MISC_CLK500_EN_MASK \
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(0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
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#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
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#define HPIPE_MISC_REFCLK_SEL_MASK \
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(0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
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#define HPIPE_RX_CONTROL_1_REG 0x140
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#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
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#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
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(0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
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#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
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#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
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(0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
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#define HPIPE_PWR_CTR_REG 0x148
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#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
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#define HPIPE_PWR_CTR_RST_DFE_MASK \
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(0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
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#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
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#define HPIPE_PWR_CTR_SFT_RST_MASK \
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(0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
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|
|
2017-04-24 15:45:28 +00:00
|
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#define HPIPE_SPD_DIV_FORCE_REG 0x154
|
2017-04-24 15:45:31 +00:00
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|
#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
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#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
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(0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
|
2017-04-24 15:45:28 +00:00
|
|
|
#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
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#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
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(0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
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#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
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#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
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(0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
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|
|
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
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#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
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(0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
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|
|
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
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#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
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(0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
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|
|
|
2016-05-23 09:12:05 +00:00
|
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|
#define HPIPE_PLLINTP_REG1 0x150
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|
#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
|
2017-04-24 15:45:31 +00:00
|
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|
#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
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#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
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|
|
(0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
|
2016-05-23 09:12:05 +00:00
|
|
|
#define HPIPE_SMAPLER_OFFSET 12
|
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|
|
#define HPIPE_SMAPLER_MASK \
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(0x1 << HPIPE_SMAPLER_OFFSET)
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|
|
|
2016-08-30 14:48:20 +00:00
|
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|
#define HPIPE_TX_REG1_REG 0x174
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|
#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
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#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
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|
|
(0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
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|
#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
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|
#define HPIPE_TX_REG1_SLC_EN_MASK \
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|
|
(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
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|
|
|
2017-04-24 15:45:26 +00:00
|
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|
#define HPIPE_PWR_CTR_DTL_REG 0x184
|
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#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
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|
|
#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
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|
|
(0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
|
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|
|
#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
|
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|
#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
|
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|
|
(0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
|
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|
|
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
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|
|
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
|
2016-05-23 09:12:05 +00:00
|
|
|
(0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
|
2017-04-24 15:45:26 +00:00
|
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|
#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
|
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|
|
#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
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|
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(0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
|
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|
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#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
|
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|
#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
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(0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
|
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|
|
#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
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|
|
#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
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|
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(0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
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|
|
#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
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|
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#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
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(1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
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|
#define HPIPE_PHASE_CONTROL_REG 0x188
|
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|
|
#define HPIPE_OS_PH_OFFSET_OFFSET 0
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|
|
#define HPIPE_OS_PH_OFFSET_MASK \
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|
|
(0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
|
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|
|
#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
|
|
|
|
#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
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|
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(0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
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|
|
#define HPIPE_OS_PH_VALID_OFFSET 8
|
|
|
|
#define HPIPE_OS_PH_VALID_MASK \
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|
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(0x1 << HPIPE_OS_PH_VALID_OFFSET)
|
2016-05-23 09:12:05 +00:00
|
|
|
|
2021-03-23 10:57:57 +00:00
|
|
|
#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
|
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|
|
#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
|
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|
|
#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
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|
|
(0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET)
|
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|
|
#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4
|
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|
|
#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \
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|
|
|
(0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET)
|
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|
|
#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8
|
|
|
|
#define HPIPE_SQ_DEGLITCH_EN_MASK \
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|
|
|
(0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET)
|
|
|
|
|
2017-04-24 15:45:31 +00:00
|
|
|
#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
|
|
|
|
#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
|
|
|
|
#define HPIPE_TRAIN_PAT_NUM_MASK \
|
|
|
|
(0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
|
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|
|
|
|
|
|
#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
|
|
|
|
#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
|
|
|
|
#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
|
|
|
|
(0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
|
|
|
|
|
|
|
|
#define HPIPE_DME_REG 0x228
|
|
|
|
#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
|
|
|
|
#define HPIPE_DME_ETHERNET_MODE_MASK \
|
|
|
|
(0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
|
|
|
|
|
2016-05-23 09:12:05 +00:00
|
|
|
#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
|
|
|
|
#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
|
|
|
|
#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
|
|
|
|
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
|
|
|
|
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
|
|
|
|
#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
|
|
|
|
#define HPIPE_TRX_TRAIN_TIMER_MASK \
|
|
|
|
(0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
|
|
|
|
|
|
|
|
#define HPIPE_PCIE_REG1 0x288
|
|
|
|
#define HPIPE_PCIE_REG3 0x290
|
|
|
|
|
|
|
|
#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
|
2017-04-24 15:45:31 +00:00
|
|
|
#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
|
|
|
|
#define HPIPE_RX_TRAIN_TIMER_MASK \
|
|
|
|
(0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
|
2016-05-23 09:12:05 +00:00
|
|
|
#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
|
|
|
|
#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
|
|
|
|
#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
|
|
|
|
#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
|
|
|
|
#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
|
|
|
|
#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
|
|
|
|
(0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
|
|
|
|
#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
|
|
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#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
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(0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
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#define HPIPE_TX_TRAIN_REG 0x31C
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#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
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#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
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(0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
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#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
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#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
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(0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
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2017-04-24 15:45:31 +00:00
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#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
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#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
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(0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
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#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
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#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
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(0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
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2016-05-23 09:12:05 +00:00
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2021-03-23 10:57:57 +00:00
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#define HPIPE_SAVED_DFE_VALUES_REG 0x328
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#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10
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#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \
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(0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
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2017-04-24 15:45:33 +00:00
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#define HPIPE_CDR_CONTROL_REG 0x418
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
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#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
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#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
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(0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
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#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
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#define HPIPE_TX_NUM_OF_PRESET_MASK \
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(0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
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#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
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#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
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(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G1_SETTINGS_3_REG 0x440
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#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
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#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
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(0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
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#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
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#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
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(0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
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#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
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#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
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(0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
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#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
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#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
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2016-08-30 14:48:20 +00:00
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(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
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#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
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(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
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#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
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#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
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(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_G1_SETTINGS_4_REG 0x444
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#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
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#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
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(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
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#define HPIPE_G2_SETTINGS_3_REG 0x448
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2017-04-24 15:45:33 +00:00
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#define HPIPE_G2_SETTINGS_4_REG 0x44c
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#define HPIPE_G2_DFE_RES_OFFSET 8
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#define HPIPE_G2_DFE_RES_MASK \
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(0x3 << HPIPE_G2_DFE_RES_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_G3_SETTING_3_REG 0x450
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2017-04-24 15:45:26 +00:00
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#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
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#define HPIPE_G3_FFE_CAP_SEL_MASK \
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(0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
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#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
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#define HPIPE_G3_FFE_RES_SEL_MASK \
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(0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
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#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
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#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
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(0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
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#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
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(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
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#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
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#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
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(0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
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#define HPIPE_G3_SETTING_4_REG 0x454
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#define HPIPE_G3_DFE_RES_OFFSET 8
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#define HPIPE_G3_DFE_RES_MASK \
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(0x3 << HPIPE_G3_DFE_RES_OFFSET)
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2017-04-24 15:45:31 +00:00
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#define HPIPE_TX_PRESET_INDEX_REG 0x468
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#define HPIPE_TX_PRESET_INDEX_OFFSET 0
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#define HPIPE_TX_PRESET_INDEX_MASK \
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(0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
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2017-04-24 15:45:33 +00:00
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#define HPIPE_DFE_CONTROL_REG 0x470
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#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
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#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
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(0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_DFE_CTRL_28_REG 0x49C
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#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
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#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
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(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
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2016-08-30 14:48:20 +00:00
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#define HPIPE_G1_SETTING_5_REG 0x538
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#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
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#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
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(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
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2017-04-24 15:45:33 +00:00
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#define HPIPE_G3_SETTING_5_REG 0x548
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#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
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#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
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(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_LANE_CONFIG0_REG 0x600
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#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
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#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
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(0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
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#define HPIPE_LANE_CONFIG1_REG 0x604
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#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
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#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
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(0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
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#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
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#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
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(0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
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#define HPIPE_LANE_STATUS1_REG 0x60C
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#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
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#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
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(0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
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#define HPIPE_LANE_CFG4_REG 0x620
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#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
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#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
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(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
|
2017-04-24 15:45:33 +00:00
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#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
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#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
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(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
|
2016-05-23 09:12:05 +00:00
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#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
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#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
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(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
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#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
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#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
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(0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
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#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
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#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
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#define HPIPE_CFG_PHY_RC_EP_MASK \
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(0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
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#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
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#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
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#define HPIPE_CFG_UPDATE_POLARITY_MASK \
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(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
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2017-04-24 15:45:33 +00:00
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#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
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#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
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#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
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(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
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#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
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#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
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(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
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#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
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#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
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(0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
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2016-05-23 09:12:05 +00:00
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#define HPIPE_RST_CLK_CTRL_REG 0x704
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#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
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#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
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(0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
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#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
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#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
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(0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
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#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
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#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
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(0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
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#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
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#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
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(0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
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#define HPIPE_TST_MODE_CTRL_REG 0x708
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#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
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#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
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(0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
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#define HPIPE_CLK_SRC_LO_REG 0x70c
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#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
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#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
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(0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
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#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
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#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
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(0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
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#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
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#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
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(0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
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#define HPIPE_CLK_SRC_HI_REG 0x710
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#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
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#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
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(0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
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#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
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#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
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(0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
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#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
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#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
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(0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
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#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
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#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
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(0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
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#define HPIPE_GLOBAL_MISC_CTRL 0x718
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#define HPIPE_GLOBAL_PM_CTRL 0x740
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#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
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#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
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(0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
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#endif /* _COMPHY_HPIPE_H_ */
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