mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-28 22:13:08 +00:00
140 lines
2.1 KiB
Text
140 lines
2.1 KiB
Text
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menu "LCRR - Clock Ratio Register register"
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if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
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choice
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prompt "DLL bypass"
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config LCRR_DBYP_UNSET
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bool "Don't set value"
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config LCRR_DBYP_PLL_ENABLED
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bool "PLL enabled"
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config LCRR_DBYP_PLL_BYPASSED
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bool "PLL bypassed"
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endchoice
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endif
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if ARCH_MPC834X || ARCH_MPC8360
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choice
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prompt "Additional delay cycles for SDRAM control signals"
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config LCRR_BUFCMDC_UNSET
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bool "Don't set value"
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config LCRR_BUFCMDC_4
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bool "4"
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config LCRR_BUFCMDC_1
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bool "1"
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config LCRR_BUFCMDC_2
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bool "2"
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config LCRR_BUFCMDC_3
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bool "3"
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endchoice
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choice
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prompt "Extended CAS latency"
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config LCRR_ECL_UNSET
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bool "Don't set value"
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config LCRR_ECL_4
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bool "4"
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config LCRR_ECL_5
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bool "5"
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config LCRR_ECL_6
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bool "6"
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config LCRR_ECL_7
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bool "7"
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endchoice
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endif # ARCH_MPC834X || ARCH_MPC8360
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if !ARCH_MPC8308
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choice
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prompt "External address delay cycles"
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config LCRR_EADC_UNSET
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bool "Don't set value"
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config LCRR_EADC_4
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bool "4"
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config LCRR_EADC_1
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bool "1"
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config LCRR_EADC_2
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bool "2"
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config LCRR_EADC_3
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bool "3"
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endchoice
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endif # !ARCH_MPC8308
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choice
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prompt "System clock divider"
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config LCRR_CLKDIV_UNSET
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bool "Don't set value"
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config LCRR_CLKDIV_2
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bool "2"
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config LCRR_CLKDIV_4
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bool "4"
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config LCRR_CLKDIV_8
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bool "8"
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endchoice
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config LCRR_DBYP
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hex
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default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
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default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
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config LCRR_BUFCMDC
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hex
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default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
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default 0x10000000 if LCRR_BUFCMDC_1
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default 0x20000000 if LCRR_BUFCMDC_2
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default 0x30000000 if LCRR_BUFCMDC_3
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config LCRR_ECL
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hex
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default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
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default 0x1000000 if LCRR_ECL_5
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default 0x2000000 if LCRR_ECL_6
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default 0x3000000 if LCRR_ECL_7
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config LCRR_EADC
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hex
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default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
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default 0x10000 if LCRR_EADC_1
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default 0x20000 if LCRR_EADC_2
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default 0x30000 if LCRR_EADC_3
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config LCRR_CLKDIV
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hex
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default 0x0 if LCRR_CLKDIV_UNSET
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default 0x2 if LCRR_CLKDIV_2
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default 0x4 if LCRR_CLKDIV_4
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default 0x8 if LCRR_CLKDIV_8
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endmenu
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