2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2007-05-13 11:58:00 +00:00
|
|
|
/*
|
2009-06-04 10:06:47 +00:00
|
|
|
* (C) Copyright 2009
|
|
|
|
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
|
|
|
*
|
2012-08-21 04:14:46 +00:00
|
|
|
* (C) Copyright 2007-2012
|
2008-11-20 07:44:42 +00:00
|
|
|
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|
|
|
*
|
|
|
|
* (C) Copyright 2003
|
|
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
2007-05-13 11:58:00 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2008-07-08 03:03:24 +00:00
|
|
|
#include <asm/processor.h>
|
2008-11-20 07:44:42 +00:00
|
|
|
#include <asm/io.h>
|
2018-08-24 19:37:14 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_CPU_SH3)
|
2018-08-24 19:43:17 +00:00
|
|
|
#define TSTR 0x2
|
|
|
|
#define TCR0 0xc
|
2018-08-24 19:37:14 +00:00
|
|
|
#endif /* CONFIG_CPU_SH3 */
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
|
2018-08-24 19:43:17 +00:00
|
|
|
#define TSTR 0x4
|
|
|
|
#define TCR0 0x10
|
2018-08-24 19:37:14 +00:00
|
|
|
#endif /* CONFIG_CPU_SH4 */
|
2012-08-21 04:14:46 +00:00
|
|
|
|
2018-08-24 19:43:17 +00:00
|
|
|
#define TCR_TPSC 0x07
|
2018-08-24 19:23:04 +00:00
|
|
|
#define TSTR_STR0 BIT(0)
|
2013-07-23 04:57:24 +00:00
|
|
|
|
2012-08-21 04:14:46 +00:00
|
|
|
int timer_init(void)
|
2007-05-13 11:58:00 +00:00
|
|
|
{
|
2018-08-24 19:43:17 +00:00
|
|
|
writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
|
|
|
|
writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
|
|
|
|
writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
|
2007-05-13 11:58:00 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|