2010-10-14 20:54:59 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2010
|
|
|
|
* ISEE 2007 SL, <www.iseebcn.com>
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2010-10-14 20:54:59 +00:00
|
|
|
*/
|
|
|
|
#include <common.h>
|
2015-01-28 14:01:32 +00:00
|
|
|
#include <status_led.h>
|
2014-10-23 03:37:15 +00:00
|
|
|
#include <dm.h>
|
|
|
|
#include <ns16550.h>
|
2010-10-14 20:54:59 +00:00
|
|
|
#include <twl4030.h>
|
2012-12-27 01:35:56 +00:00
|
|
|
#include <netdev.h>
|
2011-09-08 14:51:01 +00:00
|
|
|
#include <asm/gpio.h>
|
2012-12-27 01:35:56 +00:00
|
|
|
#include <asm/io.h>
|
2010-10-14 20:54:59 +00:00
|
|
|
#include <asm/arch/mem.h>
|
2010-11-04 19:34:33 +00:00
|
|
|
#include <asm/arch/mmc_host_def.h>
|
2010-10-14 20:54:59 +00:00
|
|
|
#include <asm/arch/mux.h>
|
|
|
|
#include <asm/arch/sys_proto.h>
|
|
|
|
#include <asm/mach-types.h>
|
2012-12-27 01:35:56 +00:00
|
|
|
#include "igep00x0.h"
|
2010-10-14 20:54:59 +00:00
|
|
|
|
2010-12-21 01:27:51 +00:00
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2012-12-27 01:35:56 +00:00
|
|
|
#if defined(CONFIG_CMD_NET)
|
2010-10-14 20:54:59 +00:00
|
|
|
/* GPMC definitions for LAN9221 chips */
|
|
|
|
static const u32 gpmc_lan_config[] = {
|
2012-12-27 01:35:56 +00:00
|
|
|
NET_LAN9221_GPMC_CONFIG1,
|
|
|
|
NET_LAN9221_GPMC_CONFIG2,
|
|
|
|
NET_LAN9221_GPMC_CONFIG3,
|
|
|
|
NET_LAN9221_GPMC_CONFIG4,
|
|
|
|
NET_LAN9221_GPMC_CONFIG5,
|
|
|
|
NET_LAN9221_GPMC_CONFIG6,
|
2010-10-14 20:54:59 +00:00
|
|
|
};
|
2012-12-27 01:35:56 +00:00
|
|
|
#endif
|
2010-10-14 20:54:59 +00:00
|
|
|
|
2014-10-23 03:37:15 +00:00
|
|
|
static const struct ns16550_platdata igep_serial = {
|
2016-03-08 03:08:49 +00:00
|
|
|
.base = OMAP34XX_UART3,
|
|
|
|
.reg_shift = 2,
|
|
|
|
.clock = V_NS16550_CLK
|
2014-10-23 03:37:15 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DEVICE(igep_uart) = {
|
2015-11-19 13:48:12 +00:00
|
|
|
"ns16550_serial",
|
2014-10-23 03:37:15 +00:00
|
|
|
&igep_serial
|
|
|
|
};
|
|
|
|
|
2010-10-14 20:54:59 +00:00
|
|
|
/*
|
|
|
|
* Routine: board_init
|
|
|
|
* Description: Early hardware init.
|
|
|
|
*/
|
|
|
|
int board_init(void)
|
|
|
|
{
|
|
|
|
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
|
|
|
/* boot param addr */
|
|
|
|
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
|
|
|
|
2015-01-28 14:01:32 +00:00
|
|
|
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
|
|
|
|
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
|
|
|
|
#endif
|
2012-12-27 03:36:01 +00:00
|
|
|
|
2015-01-28 14:01:32 +00:00
|
|
|
return 0;
|
2012-12-27 03:36:01 +00:00
|
|
|
}
|
|
|
|
|
2012-07-28 01:19:34 +00:00
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
|
|
/*
|
|
|
|
* Routine: omap_rev_string
|
|
|
|
* Description: For SPL builds output board rev
|
|
|
|
*/
|
|
|
|
void omap_rev_string(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Routine: get_board_mem_timings
|
|
|
|
* Description: If we use SPL then there is no x-loader nor config header
|
|
|
|
* so we have to setup the DDR timings ourself on both banks.
|
|
|
|
*/
|
2012-11-13 07:40:28 +00:00
|
|
|
void get_board_mem_timings(struct board_sdrc_timings *timings)
|
2012-07-28 01:19:34 +00:00
|
|
|
{
|
2012-11-13 07:40:28 +00:00
|
|
|
timings->mr = MICRON_V_MR_165;
|
2012-07-28 01:19:34 +00:00
|
|
|
#ifdef CONFIG_BOOT_NAND
|
2012-11-13 07:40:28 +00:00
|
|
|
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
|
|
|
|
timings->ctrla = MICRON_V_ACTIMA_200;
|
|
|
|
timings->ctrlb = MICRON_V_ACTIMB_200;
|
|
|
|
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
|
2012-07-28 01:19:34 +00:00
|
|
|
#else
|
|
|
|
if (get_cpu_family() == CPU_OMAP34XX) {
|
2012-11-13 07:40:28 +00:00
|
|
|
timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
|
|
|
|
timings->ctrla = NUMONYX_V_ACTIMA_165;
|
|
|
|
timings->ctrlb = NUMONYX_V_ACTIMB_165;
|
|
|
|
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
|
2012-07-28 01:19:34 +00:00
|
|
|
|
|
|
|
} else {
|
2012-11-13 07:40:28 +00:00
|
|
|
timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
|
|
|
|
timings->ctrla = NUMONYX_V_ACTIMA_200;
|
|
|
|
timings->ctrlb = NUMONYX_V_ACTIMB_200;
|
|
|
|
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
|
2012-07-28 01:19:34 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-12-27 01:35:56 +00:00
|
|
|
#if defined(CONFIG_CMD_NET)
|
2016-01-04 22:07:59 +00:00
|
|
|
|
|
|
|
static void reset_net_chip(int gpio)
|
|
|
|
{
|
|
|
|
if (!gpio_request(gpio, "eth nrst")) {
|
|
|
|
gpio_direction_output(gpio, 1);
|
|
|
|
udelay(1);
|
|
|
|
gpio_set_value(gpio, 0);
|
|
|
|
udelay(40);
|
|
|
|
gpio_set_value(gpio, 1);
|
|
|
|
mdelay(10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-10-14 20:54:59 +00:00
|
|
|
/*
|
|
|
|
* Routine: setup_net_chip
|
|
|
|
* Description: Setting up the configuration GPMC registers specific to the
|
|
|
|
* Ethernet hardware.
|
|
|
|
*/
|
|
|
|
static void setup_net_chip(void)
|
|
|
|
{
|
|
|
|
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
|
|
|
|
|
2016-01-04 22:07:59 +00:00
|
|
|
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
|
|
|
|
CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
|
2010-10-14 20:54:59 +00:00
|
|
|
|
|
|
|
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
|
|
|
|
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
|
|
|
|
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
|
|
|
|
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
|
|
|
|
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
|
|
|
|
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
|
|
|
|
&ctrl_base->gpmc_nadv_ale);
|
|
|
|
|
2016-01-04 22:07:59 +00:00
|
|
|
reset_net_chip(64);
|
2010-10-14 20:54:59 +00:00
|
|
|
}
|
2012-12-27 01:35:56 +00:00
|
|
|
#else
|
|
|
|
static inline void setup_net_chip(void) {}
|
2010-10-14 20:54:59 +00:00
|
|
|
#endif
|
|
|
|
|
2012-07-28 01:19:34 +00:00
|
|
|
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
|
2010-11-04 19:34:33 +00:00
|
|
|
int board_mmc_init(bd_t *bis)
|
|
|
|
{
|
2012-12-03 02:19:47 +00:00
|
|
|
return omap_mmc_init(0, 0, 0, -1, -1);
|
2010-11-04 19:34:33 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-11-08 19:55:47 +00:00
|
|
|
#if defined(CONFIG_GENERIC_MMC)
|
|
|
|
void board_mmc_power_init(void)
|
|
|
|
{
|
|
|
|
twl4030_power_mmc_init(0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-08-07 15:53:19 +00:00
|
|
|
void set_fdt(void)
|
|
|
|
{
|
|
|
|
switch (gd->bd->bi_arch_number) {
|
|
|
|
case MACH_TYPE_IGEP0020:
|
2015-09-07 06:28:09 +00:00
|
|
|
setenv("fdtfile", "omap3-igep0020.dtb");
|
2013-08-07 15:53:19 +00:00
|
|
|
break;
|
|
|
|
case MACH_TYPE_IGEP0030:
|
2015-09-07 06:28:09 +00:00
|
|
|
setenv("fdtfile", "omap3-igep0030.dtb");
|
2013-08-07 15:53:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-10-14 20:54:59 +00:00
|
|
|
/*
|
|
|
|
* Routine: misc_init_r
|
|
|
|
* Description: Configure board specific parts
|
|
|
|
*/
|
|
|
|
int misc_init_r(void)
|
|
|
|
{
|
|
|
|
twl4030_power_init();
|
|
|
|
|
|
|
|
setup_net_chip();
|
|
|
|
|
2015-08-27 17:37:13 +00:00
|
|
|
omap_die_id_display();
|
2010-10-14 20:54:59 +00:00
|
|
|
|
2013-08-07 15:53:19 +00:00
|
|
|
set_fdt();
|
|
|
|
|
2010-10-14 20:54:59 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Routine: set_muxconf_regs
|
|
|
|
* Description: Setting up the configuration Mux registers specific to the
|
|
|
|
* hardware. Many pins need to be moved from protect to primary
|
|
|
|
* mode.
|
|
|
|
*/
|
|
|
|
void set_muxconf_regs(void)
|
|
|
|
{
|
|
|
|
MUX_DEFAULT();
|
2012-12-27 01:35:56 +00:00
|
|
|
|
|
|
|
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
|
|
|
|
MUX_IGEP0020();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
|
|
|
|
MUX_IGEP0030();
|
|
|
|
#endif
|
2010-10-14 20:54:59 +00:00
|
|
|
}
|
|
|
|
|
2012-12-27 01:35:56 +00:00
|
|
|
#if defined(CONFIG_CMD_NET)
|
2010-10-14 20:54:59 +00:00
|
|
|
int board_eth_init(bd_t *bis)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMC911X
|
2016-01-04 22:07:59 +00:00
|
|
|
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
|
|
|
#else
|
|
|
|
return 0;
|
2010-10-14 20:54:59 +00:00
|
|
|
#endif
|
|
|
|
}
|
2012-12-27 01:35:56 +00:00
|
|
|
#endif
|