u-boot/arch/x86/include/asm/arch-broadwell/lpc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * From coreboot soc/intel/broadwell/include/soc/lpc.h
 *
 * Copyright (C) 2016 Google Inc.
 */

#ifndef _ASM_ARCH_LPC_H
#define _ASM_ARCH_LPC_H

#define GEN_PMCON_1		0xa0
#define  SMI_LOCK		(1 << 4)
#define GEN_PMCON_2		0xa2
#define  SYSTEM_RESET_STS	(1 << 4)
#define  THERMTRIP_STS		(1 << 3)
#define  SYSPWR_FLR		(1 << 1)
#define  PWROK_FLR		(1 << 0)
#define GEN_PMCON_3		0xa4
#define  SUS_PWR_FLR		(1 << 14)
#define  GEN_RST_STS		(1 << 9)
#define  RTC_BATTERY_DEAD	(1 << 2)
#define  PWR_FLR		(1 << 1)
#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
#define GEN_PMCON_LOCK		0xa6
#define  SLP_STR_POL_LOCK	(1 << 2)
#define  ACPI_BASE_LOCK		(1 << 1)
#define PMIR			0xac
#define  PMIR_CF9LOCK		(1 << 31)
#define  PMIR_CF9GR		(1 << 20)

#endif
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0 */`
x86: broadwell: Add an LPC driver Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:23 +00:00			`/*`
			`* From coreboot soc/intel/broadwell/include/soc/lpc.h`
			`*`
			`* Copyright (C) 2016 Google Inc.`
			`*/`

			`#ifndef _ASM_ARCH_LPC_H`
			`#define _ASM_ARCH_LPC_H`

			`#define GEN_PMCON_1 0xa0`
			`#define SMI_LOCK (1 << 4)`
			`#define GEN_PMCON_2 0xa2`
			`#define SYSTEM_RESET_STS (1 << 4)`
			`#define THERMTRIP_STS (1 << 3)`
			`#define SYSPWR_FLR (1 << 1)`
			`#define PWROK_FLR (1 << 0)`
			`#define GEN_PMCON_3 0xa4`
			`#define SUS_PWR_FLR (1 << 14)`
			`#define GEN_RST_STS (1 << 9)`
			`#define RTC_BATTERY_DEAD (1 << 2)`
			`#define PWR_FLR (1 << 1)`
			`#define SLEEP_AFTER_POWER_FAIL (1 << 0)`
			`#define GEN_PMCON_LOCK 0xa6`
			`#define SLP_STR_POL_LOCK (1 << 2)`
			`#define ACPI_BASE_LOCK (1 << 1)`
			`#define PMIR 0xac`
			`#define PMIR_CF9LOCK (1 << 31)`
			`#define PMIR_CF9GR (1 << 20)`

			`#endif`