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u-boot/arch/powerpc/cpu/mpc83xx/serdes.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
/*
* Freescale SerDes initialization routine
*
powerpc/mpc83xx: fix copyright string in serdes.c The misspelling of "semiconductor" causes some internal copyright analysis tools to complain. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-06-19 00:11:34 +00:00
* Copyright 2007,2011 Freescale Semiconductor, Inc.
mpc83xx/serdes: License cleanup: remove "All Rights Reserved" notice "All Rights Reserved" conflicts with the GPL. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2009-09-02 13:58:48 +00:00
* Copyright (C) 2008 MontaVista Software, Inc.
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
*
* Author: Li Yang <leoli@freescale.com>
*/
misc: Add MPC83xx serdes driver Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:46 +00:00
#ifndef CONFIG_MPC83XX_SERDES
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
#include <config.h>
#include <common.h>
#include <asm/io.h>
ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ The MPC83xx SERDES control is different from the other FSL PPC chips. For now lets split it out so we can standardize on interfaces for determining of a device on SERDES is configured. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-20 15:02:24 +00:00
#include <asm/fsl_mpc83xx_serdes.h>
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:11 +00:00
#include <linux/delay.h>
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
/* SerDes registers */
#define FSL_SRDSCR0_OFFS 0x0
#define FSL_SRDSCR0_DPP_1V2 0x00008800
powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-17 02:15:38 +00:00
#define FSL_SRDSCR0_TXEQA_MASK 0x00007000
#define FSL_SRDSCR0_TXEQA_SATA 0x00001000
#define FSL_SRDSCR0_TXEQE_MASK 0x00000700
#define FSL_SRDSCR0_TXEQE_SATA 0x00000100
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
#define FSL_SRDSCR1_OFFS 0x4
#define FSL_SRDSCR1_PLLBW 0x00000040
#define FSL_SRDSCR2_OFFS 0x8
#define FSL_SRDSCR2_VDD_1V2 0x00800000
#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
#define FSL_SRDSCR2_SEIC_SATA 0x00001414
#define FSL_SRDSCR2_SEIC_PEX 0x00001010
#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
#define FSL_SRDSCR3_OFFS 0xc
#define FSL_SRDSCR3_KFR_SATA 0x10100000
#define FSL_SRDSCR3_KPH_SATA 0x04040000
#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
#define FSL_SRDSCR4_OFFS 0x10
#define FSL_SRDSCR4_PROT_SATA 0x00000808
#define FSL_SRDSCR4_PROT_PEX 0x00000101
#define FSL_SRDSCR4_PROT_SGMII 0x00000505
#define FSL_SRDSCR4_PLANE_X2 0x01000000
#define FSL_SRDSRSTCTL_OFFS 0x20
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
mpc83xx: serdes: add forgotten shifts for rfcks The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-02 14:31:56 +00:00
void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
{
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
void *regs = (void *)CONFIG_SYS_IMMR + offset;
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
u32 tmp;
/* 1.0V corevdd */
if (vdd) {
/* DPPE/DPPA = 0 */
tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
tmp &= ~FSL_SRDSCR0_DPP_1V2;
out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
/* VDD = 0 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_VDD_1V2;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
}
/* protocol specific configuration */
switch (proto) {
case FSL_SERDES_PROTO_SATA:
/* Set and clear reset bits */
tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
tmp |= FSL_SRDSRSTCTL_SATA_RESET;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
udelay(1000);
tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-17 02:15:38 +00:00
/* Configure SRDSCR0 */
clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
/* Configure SRDSCR1 */
tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_PLLBW;
out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
/* Configure SRDSCR2 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_SEIC_MASK;
tmp |= FSL_SRDSCR2_SEIC_SATA;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
/* Configure SRDSCR3 */
tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
FSL_SRDSCR3_SDFM_SATA_PEX |
FSL_SRDSCR3_SDTXL_SATA;
out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
/* Configure SRDSCR4 */
tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
break;
case FSL_SERDES_PROTO_PEX:
case FSL_SERDES_PROTO_PEX_X2:
/* Configure SRDSCR1 */
tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
tmp |= FSL_SRDSCR1_PLLBW;
out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
/* Configure SRDSCR2 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_SEIC_MASK;
tmp |= FSL_SRDSCR2_SEIC_PEX;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
/* Configure SRDSCR3 */
tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
/* Configure SRDSCR4 */
tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
if (proto == FSL_SERDES_PROTO_PEX_X2)
tmp |= FSL_SRDSCR4_PLANE_X2;
out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
break;
case FSL_SERDES_PROTO_SGMII:
/* Configure SRDSCR1 */
tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_PLLBW;
out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
/* Configure SRDSCR2 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_SEIC_MASK;
tmp |= FSL_SRDSCR2_SEIC_SGMII;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
/* Configure SRDSCR3 */
out_be32(regs + FSL_SRDSCR3_OFFS, 0);
/* Configure SRDSCR4 */
tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
break;
default:
return;
}
/* Do a software reset */
tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
tmp |= FSL_SRDSRSTCTL_RST;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
}
misc: Add MPC83xx serdes driver Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:46 +00:00
#endif /* !CONFIG_MPC83XX_SERDES */
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