mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
457 lines
13 KiB
C
457 lines
13 KiB
C
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/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_HDMI_H
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#define _ASM_ARCH_HDMI_H
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#define HDMI_EDID_BLOCK_SIZE 128
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struct rk3288_hdmi {
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u32 reserved0[0x100];
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u32 ih_fc_stat0;
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u32 ih_fc_stat1;
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u32 ih_fc_stat2;
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u32 ih_as_stat0;
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u32 ih_phy_stat0;
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u32 ih_i2cm_stat0;
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u32 ih_cec_stat0;
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u32 ih_vp_stat0;
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u32 ih_i2cmphy_stat0;
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u32 ih_ahbdmaaud_stat0;
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u32 reserved1[0x17f-0x109];
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u32 ih_mute_fc_stat0;
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u32 ih_mute_fc_stat1;
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u32 ih_mute_fc_stat2;
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u32 ih_mute_as_stat0;
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u32 ih_mute_phy_stat0;
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u32 ih_mute_i2cm_stat0;
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u32 ih_mute_cec_stat0;
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u32 ih_mute_vp_stat0;
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u32 ih_mute_i2cmphy_stat0;
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u32 ih_mute_ahbdmaaud_stat0;
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u32 reserved2[0x1fe - 0x189];
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u32 ih_mute;
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u32 tx_invid0;
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u32 tx_instuffing;
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u32 tx_gydata0;
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u32 tx_gydata1;
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u32 tx_rcrdata0;
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u32 tx_rcrdata1;
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u32 tx_bcbdata0;
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u32 tx_bcbdata1;
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u32 reserved3[0x7ff-0x207];
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u32 vp_status;
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u32 vp_pr_cd;
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u32 vp_stuff;
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u32 vp_remap;
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u32 vp_conf;
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u32 vp_stat;
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u32 vp_int;
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u32 vp_mask;
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u32 vp_pol;
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u32 reserved4[0xfff-0x808];
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u32 fc_invidconf;
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u32 fc_inhactv0;
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u32 fc_inhactv1;
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u32 fc_inhblank0;
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u32 fc_inhblank1;
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u32 fc_invactv0;
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u32 fc_invactv1;
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u32 fc_invblank;
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u32 fc_hsyncindelay0;
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u32 fc_hsyncindelay1;
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u32 fc_hsyncinwidth0;
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u32 fc_hsyncinwidth1;
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u32 fc_vsyncindelay;
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u32 fc_vsyncinwidth;
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u32 fc_infreq0;
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u32 fc_infreq1;
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u32 fc_infreq2;
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u32 fc_ctrldur;
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u32 fc_exctrldur;
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u32 fc_exctrlspac;
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u32 fc_ch0pream;
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u32 fc_ch1pream;
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u32 fc_ch2pream;
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u32 fc_aviconf3;
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u32 fc_gcp;
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u32 fc_aviconf0;
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u32 fc_aviconf1;
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u32 fc_aviconf2;
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u32 fc_avivid;
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u32 fc_avietb0;
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u32 fc_avietb1;
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u32 fc_avisbb0;
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u32 fc_avisbb1;
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u32 fc_avielb0;
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u32 fc_avielb1;
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u32 fc_avisrb0;
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u32 fc_avisrb1;
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u32 fc_audiconf0;
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u32 fc_audiconf1;
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u32 fc_audiconf2;
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u32 fc_audiconf3;
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u32 fc_vsdieeeid0;
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u32 fc_vsdsize;
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u32 reserved7[0x2fff-0x102a];
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u32 phy_conf0;
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u32 phy_tst0;
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u32 phy_tst1;
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u32 phy_tst2;
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u32 phy_stat0;
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u32 phy_int0;
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u32 phy_mask0;
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u32 phy_pol0;
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u32 reserved8[0x301f-0x3007];
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u32 phy_i2cm_slave_addr;
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u32 phy_i2cm_address_addr;
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u32 phy_i2cm_datao_1_addr;
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u32 phy_i2cm_datao_0_addr;
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u32 phy_i2cm_datai_1_addr;
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u32 phy_i2cm_datai_0_addr;
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u32 phy_i2cm_operation_addr;
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u32 phy_i2cm_int_addr;
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u32 phy_i2cm_ctlint_addr;
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u32 phy_i2cm_div_addr;
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u32 phy_i2cm_softrstz_addr;
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u32 phy_i2cm_ss_scl_hcnt_1_addr;
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u32 phy_i2cm_ss_scl_hcnt_0_addr;
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u32 phy_i2cm_ss_scl_lcnt_1_addr;
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u32 phy_i2cm_ss_scl_lcnt_0_addr;
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u32 phy_i2cm_fs_scl_hcnt_1_addr;
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u32 phy_i2cm_fs_scl_hcnt_0_addr;
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u32 phy_i2cm_fs_scl_lcnt_1_addr;
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u32 phy_i2cm_fs_scl_lcnt_0_addr;
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u32 reserved9[0x30ff-0x3032];
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u32 aud_conf0;
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u32 aud_conf1;
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u32 aud_int;
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u32 aud_conf2;
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u32 aud_int1;
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u32 reserved32[0x31ff-0x3104];
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u32 aud_n1;
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u32 aud_n2;
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u32 aud_n3;
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u32 aud_cts1;
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u32 aud_cts2;
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u32 aud_cts3;
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u32 aud_inputclkfs;
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u32 reserved12[0x3fff-0x3206];
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u32 mc_sfrdiv;
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u32 mc_clkdis;
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u32 mc_swrstz;
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u32 mc_opctrl;
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u32 mc_flowctrl;
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u32 mc_phyrstz;
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u32 mc_lockonclock;
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u32 mc_heacphy_rst;
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u32 reserved13[0x40ff-0x4007];
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u32 csc_cfg;
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u32 csc_scale;
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struct {
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u32 msb;
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u32 lsb;
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} csc_coef[3][4];
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u32 reserved17[0x7dff-0x4119];
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u32 i2cm_slave;
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u32 i2c_address;
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u32 i2cm_datao;
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u32 i2cm_datai;
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u32 i2cm_operation;
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u32 i2cm_int;
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u32 i2cm_ctlint;
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u32 i2cm_div;
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u32 i2cm_segaddr;
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u32 i2cm_softrstz;
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u32 i2cm_segptr;
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u32 i2cm_ss_scl_hcnt_1_addr;
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u32 i2cm_ss_scl_hcnt_0_addr;
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u32 i2cm_ss_scl_lcnt_1_addr;
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u32 i2cm_ss_scl_lcnt_0_addr;
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u32 i2cm_fs_scl_hcnt_1_addr;
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u32 i2cm_fs_scl_hcnt_0_addr;
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u32 i2cm_fs_scl_lcnt_1_addr;
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u32 i2cm_fs_scl_lcnt_0_addr;
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u32 reserved18[0x7e1f-0x7e12];
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u32 i2cm_buf0;
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};
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check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
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enum {
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/* HDMI PHY registers define */
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PHY_OPMODE_PLLCFG = 0x06,
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PHY_CKCALCTRL = 0x05,
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PHY_CKSYMTXCTRL = 0x09,
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PHY_VLEVCTRL = 0x0e,
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PHY_PLLCURRCTRL = 0x10,
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PHY_PLLPHBYCTRL = 0x13,
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PHY_PLLGMPCTRL = 0x15,
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PHY_PLLCLKBISTPHASE = 0x17,
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PHY_TXTERM = 0x19,
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/* ih_phy_stat0 field values */
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HDMI_IH_PHY_STAT0_HPD = 0x1,
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/* ih_mute field values */
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HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
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HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
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/* tx_invid0 field values */
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HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
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HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
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HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
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/* tx_instuffing field values */
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HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
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HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
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HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
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/* vp_pr_cd field values */
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HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
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HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
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HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
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HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
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/* vp_stuff field values */
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HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
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HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
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HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
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HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
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HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
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HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
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HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
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HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
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/* vp_conf field values */
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HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
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HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
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HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
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HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
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HDMI_VP_CONF_PR_EN_MASK = 0x10,
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HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
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HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
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HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
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HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
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HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
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HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
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HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
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/* vp_remap field values */
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HDMI_VP_REMAP_YCC422_16BIT = 0x0,
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/* fc_invidconf field values */
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
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HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
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HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
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HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
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HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
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HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
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HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
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HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
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HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
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HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
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HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
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HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
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HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
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HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
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HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
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HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
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HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
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HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
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HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
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/* fc_aviconf0-fc_aviconf3 field values */
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HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
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HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
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HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
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HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
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HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
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HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
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HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
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HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
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HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
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HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
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HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
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HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
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HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
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HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
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HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
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HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
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HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
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HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
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HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
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HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
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HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
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HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
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HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
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HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
|
||
|
|
HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
|
||
|
|
HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
|
||
|
|
HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
|
||
|
|
HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
|
||
|
|
HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
|
||
|
|
HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
|
||
|
|
|
||
|
|
HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
|
||
|
|
HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
|
||
|
|
HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
|
||
|
|
HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
|
||
|
|
HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
|
||
|
|
HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
|
||
|
|
HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
|
||
|
|
HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
|
||
|
|
HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
|
||
|
|
HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
|
||
|
|
HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
|
||
|
|
HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
|
||
|
|
HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
|
||
|
|
HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
|
||
|
|
HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
|
||
|
|
HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
|
||
|
|
HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
|
||
|
|
HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
|
||
|
|
|
||
|
|
HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
|
||
|
|
HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
|
||
|
|
HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
|
||
|
|
HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
|
||
|
|
HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
|
||
|
|
HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
|
||
|
|
HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
|
||
|
|
HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
|
||
|
|
|
||
|
|
/* fc_gcp field values*/
|
||
|
|
HDMI_FC_GCP_SET_AVMUTE = 0x02,
|
||
|
|
HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
|
||
|
|
|
||
|
|
/* phy_conf0 field values */
|
||
|
|
HDMI_PHY_CONF0_PDZ_MASK = 0x80,
|
||
|
|
HDMI_PHY_CONF0_PDZ_OFFSET = 7,
|
||
|
|
HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
|
||
|
|
HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
|
||
|
|
HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
|
||
|
|
HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
|
||
|
|
HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
|
||
|
|
HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
|
||
|
|
HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
|
||
|
|
HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
|
||
|
|
HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
|
||
|
|
HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
|
||
|
|
HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
|
||
|
|
HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
|
||
|
|
|
||
|
|
/* phy_tst0 field values */
|
||
|
|
HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
|
||
|
|
HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
|
||
|
|
|
||
|
|
/* phy_stat0 field values */
|
||
|
|
HDMI_PHY_HPD = 0x02,
|
||
|
|
HDMI_PHY_TX_PHY_LOCK = 0x01,
|
||
|
|
|
||
|
|
/* phy_i2cm_slave_addr field values */
|
||
|
|
HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
|
||
|
|
|
||
|
|
/* phy_i2cm_operation_addr field values */
|
||
|
|
HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
|
||
|
|
|
||
|
|
/* hdmi_phy_i2cm_int_addr */
|
||
|
|
HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
|
||
|
|
|
||
|
|
/* hdmi_phy_i2cm_ctlint_addr */
|
||
|
|
HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
|
||
|
|
HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
|
||
|
|
|
||
|
|
/* aud_conf0 field values */
|
||
|
|
HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
|
||
|
|
HDMI_AUD_CONF0_I2S_SELECT = 0x20,
|
||
|
|
HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
|
||
|
|
HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
|
||
|
|
HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
|
||
|
|
HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
|
||
|
|
|
||
|
|
/* aud_conf0 field values */
|
||
|
|
HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
|
||
|
|
HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
|
||
|
|
|
||
|
|
/* aud_n3 field values */
|
||
|
|
HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
|
||
|
|
HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
|
||
|
|
|
||
|
|
/* aud_cts3 field values */
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_1 = 0,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
|
||
|
|
HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
|
||
|
|
HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
|
||
|
|
HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
|
||
|
|
|
||
|
|
/* aud_inputclkfs filed values */
|
||
|
|
HDMI_AUD_INPUTCLKFS_128 = 0x0,
|
||
|
|
|
||
|
|
/* mc_clkdis field values */
|
||
|
|
HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
|
||
|
|
HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
|
||
|
|
HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
|
||
|
|
|
||
|
|
/* mc_swrstz field values */
|
||
|
|
HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
|
||
|
|
HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
|
||
|
|
|
||
|
|
/* mc_flowctrl field values */
|
||
|
|
HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
|
||
|
|
HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
|
||
|
|
|
||
|
|
/* mc_phyrstz field values */
|
||
|
|
HDMI_MC_PHYRSTZ_ASSERT = 0x0,
|
||
|
|
HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
|
||
|
|
|
||
|
|
/* mc_heacphy_rst field values */
|
||
|
|
HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
|
||
|
|
|
||
|
|
/* csc_cfg field values */
|
||
|
|
HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
|
||
|
|
|
||
|
|
/* csc_scale field values */
|
||
|
|
HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
|
||
|
|
HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
|
||
|
|
HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
|
||
|
|
HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
|
||
|
|
HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
|
||
|
|
HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
|
||
|
|
|
||
|
|
/* i2cm filed values */
|
||
|
|
HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
|
||
|
|
HDMI_I2CM_SEGADDR_DDC = 0x30,
|
||
|
|
HDMI_I2CM_OPT_RD8_EXT = 0x8,
|
||
|
|
HDMI_I2CM_OPT_RD8 = 0x4,
|
||
|
|
HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
|
||
|
|
HDMI_I2CM_DIV_FAST_MODE = 0x8,
|
||
|
|
HDMI_I2CM_DIV_STD_MODE = 0x0,
|
||
|
|
HDMI_I2CM_SOFTRSTZ = 0x1,
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
struct display_timing;
|
||
|
|
struct rk3288_grf;
|
||
|
|
|
||
|
|
int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
|
||
|
|
int rk_hdmi_enable(const struct display_timing *edid);
|
||
|
|
int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif
|