2011-11-02 00:29:27 +00:00
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/*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-11-02 00:29:27 +00:00
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*/
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#ifndef __REGS_MMC_H__
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#define __REGS_MMC_H__
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#define MMC0_BASE 0x41100000
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#define MMC1_BASE 0x42000000
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int pxa_mmc_register(int card_index);
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struct pxa_mmc_regs {
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uint32_t strpcl;
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uint32_t stat;
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uint32_t clkrt;
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uint32_t spi;
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uint32_t cmdat;
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uint32_t resto;
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uint32_t rdto;
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uint32_t blklen;
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uint32_t nob;
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uint32_t prtbuf;
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uint32_t i_mask;
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uint32_t i_reg;
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uint32_t cmd;
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uint32_t argh;
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uint32_t argl;
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uint32_t res;
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uint32_t rxfifo;
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uint32_t txfifo;
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};
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/* MMC_STRPCL */
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#define MMC_STRPCL_STOP_CLK (1 << 0)
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#define MMC_STRPCL_START_CLK (1 << 1)
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/* MMC_STAT */
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#define MMC_STAT_END_CMD_RES (1 << 13)
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#define MMC_STAT_PRG_DONE (1 << 12)
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#define MMC_STAT_DATA_TRAN_DONE (1 << 11)
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#define MMC_STAT_CLK_EN (1 << 8)
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#define MMC_STAT_RECV_FIFO_FULL (1 << 7)
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#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6)
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#define MMC_STAT_RES_CRC_ERROR (1 << 5)
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#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4)
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#define MMC_STAT_CRC_READ_ERROR (1 << 3)
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#define MMC_STAT_CRC_WRITE_ERROR (1 << 2)
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#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1)
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#define MMC_STAT_READ_TIME_OUT (1 << 0)
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/* MMC_CLKRT */
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#define MMC_CLKRT_20MHZ 0
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#define MMC_CLKRT_10MHZ 1
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#define MMC_CLKRT_5MHZ 2
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#define MMC_CLKRT_2_5MHZ 3
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#define MMC_CLKRT_1_25MHZ 4
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#define MMC_CLKRT_0_625MHZ 5
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#define MMC_CLKRT_0_3125MHZ 6
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/* MMC_SPI */
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#define MMC_SPI_EN (1 << 0)
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#define MMC_SPI_CS_EN (1 << 2)
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#define MMC_SPI_CS_ADDRESS (1 << 3)
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#define MMC_SPI_CRC_ON (1 << 1)
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/* MMC_CMDAT */
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#define MMC_CMDAT_SD_4DAT (1 << 8)
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#define MMC_CMDAT_MMC_DMA_EN (1 << 7)
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#define MMC_CMDAT_INIT (1 << 6)
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#define MMC_CMDAT_BUSY (1 << 5)
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#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT)
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#define MMC_CMDAT_STREAM (1 << 4)
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#define MMC_CMDAT_WRITE (1 << 3)
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#define MMC_CMDAT_DATA_EN (1 << 2)
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#define MMC_CMDAT_R0 0
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#define MMC_CMDAT_R1 1
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#define MMC_CMDAT_R2 2
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#define MMC_CMDAT_R3 3
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/* MMC_RESTO */
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#define MMC_RES_TO_MAX_MASK 0x7f
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/* MMC_RDTO */
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#define MMC_READ_TO_MAX_MASK 0xffff
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/* MMC_BLKLEN */
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#define MMC_BLK_LEN_MAX_MASK 0x3ff
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/* MMC_PRTBUF */
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#define MMC_PRTBUF_BUF_PART_FULL (1 << 0)
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/* MMC_I_MASK */
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#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6)
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#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5)
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#define MMC_I_MASK_CLK_IS_OFF (1 << 4)
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#define MMC_I_MASK_STOP_CMD (1 << 3)
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#define MMC_I_MASK_END_CMD_RES (1 << 2)
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#define MMC_I_MASK_PRG_DONE (1 << 1)
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#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0)
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#define MMC_I_MASK_ALL 0x7f
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/* MMC_I_REG */
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#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6)
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#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5)
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#define MMC_I_REG_CLK_IS_OFF (1 << 4)
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#define MMC_I_REG_STOP_CMD (1 << 3)
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#define MMC_I_REG_END_CMD_RES (1 << 2)
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#define MMC_I_REG_PRG_DONE (1 << 1)
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#define MMC_I_REG_DATA_TRAN_DONE (1 << 0)
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/* MMC_CMD */
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#define MMC_CMD_INDEX_MAX 0x6f
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#define MMC_R1_IDLE_STATE 0x01
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#define MMC_R1_ERASE_STATE 0x02
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#define MMC_R1_ILLEGAL_CMD 0x04
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#define MMC_R1_COM_CRC_ERR 0x08
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#define MMC_R1_ERASE_SEQ_ERR 0x01
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#define MMC_R1_ADDR_ERR 0x02
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#define MMC_R1_PARAM_ERR 0x04
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#define MMC_R1B_WP_ERASE_SKIP 0x0002
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#define MMC_R1B_ERR 0x0004
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#define MMC_R1B_CC_ERR 0x0008
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#define MMC_R1B_CARD_ECC_ERR 0x0010
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#define MMC_R1B_WP_VIOLATION 0x0020
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#define MMC_R1B_ERASE_PARAM 0x0040
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#define MMC_R1B_OOR 0x0080
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#define MMC_R1B_IDLE_STATE 0x0100
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#define MMC_R1B_ERASE_RESET 0x0200
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#define MMC_R1B_ILLEGAL_CMD 0x0400
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#define MMC_R1B_COM_CRC_ERR 0x0800
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#define MMC_R1B_ERASE_SEQ_ERR 0x1000
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#define MMC_R1B_ADDR_ERR 0x2000
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#define MMC_R1B_PARAM_ERR 0x4000
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#endif /* __REGS_MMC_H__ */
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