u-boot/include/dt-bindings/clock/ast2500-scu.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2016 Google Inc.
 */

/* Core Clocks */
#define PLL_HPLL	1
#define PLL_DPLL	2
#define PLL_D2PLL	3
#define PLL_MPLL	4
#define ARMCLK		5


/* Bus Clocks, derived from core clocks */
#define BCLK_PCLK	101
#define BCLK_LHCLK	102
#define BCLK_MACCLK	103
#define BCLK_SDCLK	104
#define BCLK_ARMCLK	105

#define MCLK_DDR	201

/* Special clocks */
#define PCLK_UART1	501
#define PCLK_UART2	502
#define PCLK_UART3	503
#define PCLK_UART4	504
#define PCLK_UART5	505
#define PCLK_MAC1	506
#define PCLK_MAC2	507
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org> 2017-01-18 21:44:56 +00:00			`/*`
			`* Copyright 2016 Google Inc.`
			`*/`

			`/* Core Clocks */`
			`#define PLL_HPLL 1`
			`#define PLL_DPLL 2`
			`#define PLL_D2PLL 3`
			`#define PLL_MPLL 4`
			`#define ARMCLK 5`


			`/* Bus Clocks, derived from core clocks */`
			`#define BCLK_PCLK 101`
			`#define BCLK_LHCLK 102`
			`#define BCLK_MACCLK 103`
			`#define BCLK_SDCLK 104`
			`#define BCLK_ARMCLK 105`

			`#define MCLK_DDR 201`

			`/* Special clocks */`
			`#define PCLK_UART1 501`
			`#define PCLK_UART2 502`
			`#define PCLK_UART3 503`
			`#define PCLK_UART4 504`
			`#define PCLK_UART5 505`
aspeed: Add support for Clocks needed by MACs Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> 2017-04-17 19:00:32 +00:00			`#define PCLK_MAC1 506`
			`#define PCLK_MAC2 507`