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u-boot/arch/arm/dts/ast2600.dtsi

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ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
model = "Aspeed BMC";
compatible = "aspeed,ast2600";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
serial9 = &uart10;
serial10 = &uart11;
serial11 = &uart12;
serial12 = &uart13;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "aspeed,ast2600-smp";
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
video_memory: video {
size = <0x04000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
no-map;
};
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges;
gic: interrupt-controller@40461000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
reg = <0x40461000 0x1000>,
<0x40462000 0x1000>,
<0x40464000 0x2000>,
<0x40466000 0x2000>;
};
ahbc: ahbc@1e600000 {
compatible = "aspeed,aspeed-ahbc";
reg = < 0x1e600000 0x100>;
};
ARM: dts: ast2600: Add PWM to device tree Add the PWM node and enable it for AST2600 EVB Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-08 03:04:07 +00:00
pwm_tach: pwm_tach@1e610000 {
compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
reg = <0x1e610000 0x100>;
clocks = <&scu ASPEED_CLK_AHB>;
resets = <&rst ASPEED_RESET_PWM>;
pwm: pwm {
compatible = "aspeed,ast2600-pwm";
#pwm-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
fmc: flash-controller@1e620000 {
reg = < 0x1e620000 0xc4
0x20000000 0x10000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
status = "disabled";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <3>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi1: flash-controller@1e630000 {
reg = < 0x1e630000 0xc4
0x30000000 0x08000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <2>;
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi2: flash-controller@1e631000 {
reg = < 0x1e631000 0xc4
0x50000000 0x08000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <3>;
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
ARM: dts: ast2600: Add HACE to device tree Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-10-27 06:17:28 +00:00
hace: hace@1e6d0000 {
compatible = "aspeed,ast2600-hace";
reg = <0x1e6d0000 0x200>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_YCLK>;
status = "disabled";
};
ARM: dts: ast2600: Add ACRY to device tree Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-10-27 06:17:31 +00:00
acry: acry@1e6fa000 {
compatible = "aspeed,ast2600-acry";
reg = <0x1e6fa000 0x1000>,
<0x1e710000 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
status = "disabled";
};
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
ARM: dts: ast2600: Add MDIO devices There are 4 MDIO bus controllers in AST2600 SOC. Each of them can connect to one or more PHY chips and is flexible to work with the 4 MAC devices in AST2600. On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY chips used by MAC 0,1,2,3 respectively. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-09 02:12:26 +00:00
mdio: bus@1e650000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e650000 0x100>;
mdio0: mdio@0 {
compatible = "aspeed,ast2600-mdio";
reg = <0 0x8>;
resets = <&rst ASPEED_RESET_MII>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio1_default>;
status = "disabled";
};
mdio1: mdio@8 {
compatible = "aspeed,ast2600-mdio";
reg = <0x8 0x8>;
resets = <&rst ASPEED_RESET_MII>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio2_default>;
status = "disabled";
};
mdio2: mdio@10 {
compatible = "aspeed,ast2600-mdio";
reg = <0x10 0x8>;
resets = <&rst ASPEED_RESET_MII>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio3_default>;
status = "disabled";
};
mdio3: mdio@18 {
compatible = "aspeed,ast2600-mdio";
reg = <0x18 0x8>;
resets = <&rst ASPEED_RESET_MII>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio4_default>;
status = "disabled";
};
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
mac0: ftgmac@1e660000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
mac1: ftgmac@1e680000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
mac2: ftgmac@1e670000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
status = "disabled";
};
mac3: ftgmac@1e690000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
status = "disabled";
};
ehci0: usb@1e6a1000 {
compatible = "aspeed,aspeed-ehci", "usb-ehci";
reg = <0x1e6a1000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ah_default>;
status = "disabled";
};
ehci1: usb@1e6a3000 {
compatible = "aspeed,aspeed-ehci", "usb-ehci";
reg = <0x1e6a3000 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2bh_default>;
status = "disabled";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon: syscon@1e6e2000 {
compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,g6-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
vga_scratch: scratch {
compatible = "aspeed,bmc-misc";
};
scu_ic0: interrupt-controller@0 {
#interrupt-cells = <1>;
compatible = "aspeed,ast2600-scu-ic";
reg = <0x560 0x10>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
scu_ic1: interrupt-controller@1 {
#interrupt-cells = <1>;
compatible = "aspeed,ast2600-scu-ic";
reg = <0x570 0x10>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
};
smp-memram@0 {
compatible = "aspeed,ast2600-smpmem", "syscon";
reg = <0x1e6e2180 0x40>;
};
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
};
pcie_bridge0: pcie@1e6ed000 {
compatible = "aspeed,ast2600-pcie";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x1e6ed000 0x100>;
ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
<0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
device_type = "pci";
bus-range = <0x00 0xff>;
resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
cfg-handle = <&pcie_cfg0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0rc_default>;
status = "disabled";
};
pcie_bridge1: pcie@1e6ed200 {
compatible = "aspeed,ast2600-pcie";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x1e6ed200 0x100>;
ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
<0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
device_type = "pci";
bus-range = <0x00 0xff>;
resets = <&rst ASPEED_RESET_PCIE_RC_O>;
cfg-handle = <&pcie_cfg1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1rc_default>;
status = "disabled";
};
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
sdc: sdc@1e740000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e740000 0x100>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
#address-cells = <1>;
#size-cells = <1>;
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
ranges = <0 0x1e740000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
reg = <0x100 0x100>;
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
reg = <0x200 0x100>;
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
emmc_controller: sdc@1e750000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e750000 0x100>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
#address-cells = <1>;
#size-cells = <1>;
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
ranges = <0 0x1e750000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>;
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
emmc: sdhci@1e750100 {
compatible = "aspeed,ast2600-sdhci";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
reg = <0x100 0x100>;
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
sdhci,auto-cmd12;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_EMMC>;
ARM: dts: ast2600: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:28 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
};
h2x: h2x@1e770000 {
compatible = "aspeed,ast2600-h2x";
reg = <0x1e770000 0x100>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_H2X>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e770000 0x100>;
status = "disabled";
pcie_cfg0: cfg0@80 {
reg = <0x80 0x80>;
compatible = "aspeed,ast2600-pcie-cfg";
};
pcie_cfg1: cfg1@C0 {
compatible = "aspeed,ast2600-pcie-cfg";
reg = <0xC0 0x80>;
};
};
gpio0: gpio@1e780000 {
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
gpio-ranges = <&pinctrl 0 0 220>;
ngpios = <208>;
};
gpio1: gpio@1e780800 {
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780800 0x800>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
gpio-ranges = <&pinctrl 0 0 208>;
ngpios = <36>;
};
uart1: serial@1e783000 {
compatible = "ns16550a";
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart5: serial@1e784000 {
compatible = "ns16550a";
reg = <0x1e784000 0x1000>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
ARM: dts: ast2600: Make WDT by default disabled The WDT devices described in the general .dtsi file should be marked as "disabled" by default. A WDT should be then enabled in the board specific .dts file on demands. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-09-16 06:10:09 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
ARM: dts: ast2600: Make WDT by default disabled The WDT devices described in the general .dtsi file should be marked as "disabled" by default. A WDT should be then enabled in the board specific .dts file on demands. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-09-16 06:10:09 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
ARM: dts: ast2600: Make WDT by default disabled The WDT devices described in the general .dtsi file should be marked as "disabled" by default. A WDT should be then enabled in the board specific .dts file on demands. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-09-16 06:10:09 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
wdt4: watchdog@1e7850C0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
ARM: dts: ast2600: Make WDT by default disabled The WDT devices described in the general .dtsi file should be marked as "disabled" by default. A WDT should be then enabled in the board specific .dts file on demands. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-09-16 06:10:09 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
lpc: lpc@1e789000 {
compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
kcs1: kcs1@0 {
compatible = "aspeed,ast2600-kcs-bmc";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
kcs_chan = <1>;
kcs_addr = <0xCA0>;
status = "disabled";
};
kcs2: kcs2@0 {
compatible = "aspeed,ast2600-kcs-bmc";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
kcs_chan = <2>;
kcs_addr = <0xCA8>;
status = "disabled";
};
kcs3: kcs3@0 {
compatible = "aspeed,ast2600-kcs-bmc";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
kcs_chan = <3>;
kcs_addr = <0xCA2>;
};
kcs4: kcs4@0 {
compatible = "aspeed,ast2600-kcs-bmc";
reg = <0x0 0x120>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
kcs_chan = <4>;
kcs_addr = <0xCA4>;
status = "disabled";
};
lpc_ctrl: lpc-ctrl@80 {
compatible = "aspeed,ast2600-lpc-ctrl";
reg = <0x80 0x80>;
status = "disabled";
};
lpc_snoop: lpc-snoop@80 {
compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x80 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
lhc: lhc@a0 {
compatible = "aspeed,ast2600-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
};
lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2600-lpc-reset";
reg = <0x98 0x4>;
#reset-cells = <1>;
status = "disabled";
};
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sio_regs: regs {
compatible = "aspeed,bmc-misc";
};
mbox: mbox@200 {
compatible = "aspeed,ast2600-mbox";
reg = <0x200 0x5c>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
status = "disabled";
};
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart3: serial@1e78e000 {
compatible = "ns16550a";
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart4: serial@1e78f000 {
compatible = "ns16550a";
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e78a000 0x1000>;
};
fsim0: fsi@1e79b000 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b000 0x94>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi1_default>;
clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
fsim1: fsi@1e79b100 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b100 0x94>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi2_default>;
clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
uart6: serial@1e790000 {
compatible = "ns16550a";
reg = <0x1e790000 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart7: serial@1e790100 {
compatible = "ns16550a";
reg = <0x1e790100 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart8: serial@1e790200 {
compatible = "ns16550a";
reg = <0x1e790200 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart9: serial@1e790300 {
compatible = "ns16550a";
reg = <0x1e790300 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart10: serial@1e790400 {
compatible = "ns16550a";
reg = <0x1e790400 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart11: serial@1e790500 {
compatible = "ns16550a";
reg = <0x1e790400 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart12: serial@1e790600 {
compatible = "ns16550a";
reg = <0x1e790600 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
uart13: serial@1e790700 {
compatible = "ns16550a";
reg = <0x1e790700 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
clock-frequency = <1846154>;
no-loopback-test;
status = "disabled";
};
display_port: dp@1e6eb000 {
compatible = "aspeed,ast2600-displayport";
reg = <0x1e6eb000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
status = "disabled";
};
};
};
};
&i2c {
i2cglobal: i2cg@00 {
compatible = "aspeed,ast2600-i2c-global";
reg = <0x0 0x40>;
resets = <&rst ASPEED_RESET_I2C>;
#if 0
new-mode;
#endif
};
i2c0: i2c@80 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80 0xC00 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c1: i2c@100 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x100 0x80 0xC20 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c2: i2c@180 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x180 0x80 0xC40 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c3: i2c@200 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x200 0x40 0xC60 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c4: i2c@280 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x280 0x80 0xC80 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c5: i2c@300 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x300 0x40 0xCA0 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c6: i2c@380 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x380 0x80 0xCC0 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c7: i2c@400 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x400 0x80 0xCE0 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c8: i2c@480 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x480 0x80 0xD00 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
ARM: dts: ast2600: Disable I2C nodes by default Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:33 +00:00
status = "disabled";
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
};
i2c9: i2c@500 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x500 0x80 0xD20 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c10: i2c@580 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x580 0x80 0xD40 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c11: i2c@600 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x600 0x80 0xD60 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c12_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c12: i2c@680 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x680 0x80 0xD80 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c13_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c13: i2c@700 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x700 0x80 0xDA0 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c14_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c14: i2c@780 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x780 0x80 0xDC0 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c15_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
i2c15: i2c@800 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x800 0x80 0xDE0 0x20>;
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: ast2600: Add I2C reset properties The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-06-23 05:10:32 +00:00
resets = <&rst ASPEED_RESET_I2C>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
clocks = <&scu ASPEED_CLK_APB2>;
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c16_default>;
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
status = "disabled";
};
};
&pinctrl {
pinctrl_fmcquad_default: fmcquad_default {
function = "FMCQUAD";
groups = "FMCQUAD";
};
pinctrl_spi1_default: spi1_default {
function = "SPI1";
groups = "SPI1";
};
pinctrl_spi1abr_default: spi1abr_default {
function = "SPI1ABR";
groups = "SPI1ABR";
};
pinctrl_spi1cs1_default: spi1cs1_default {
function = "SPI1CS1";
groups = "SPI1CS1";
};
pinctrl_spi1wp_default: spi1wp_default {
function = "SPI1WP";
groups = "SPI1WP";
};
pinctrl_spi1quad_default: spi1quad_default {
function = "SPI1QUAD";
groups = "SPI1QUAD";
};
pinctrl_spi2_default: spi2_default {
function = "SPI2";
groups = "SPI2";
};
pinctrl_spi2cs1_default: spi2cs1_default {
function = "SPI2CS1";
groups = "SPI2CS1";
};
pinctrl_spi2cs2_default: spi2cs2_default {
function = "SPI2CS2";
groups = "SPI2CS2";
};
pinctrl_spi2quad_default: spi2quad_default {
function = "SPI2QUAD";
groups = "SPI2QUAD";
};
pinctrl_acpi_default: acpi_default {
function = "ACPI";
groups = "ACPI";
};
pinctrl_adc0_default: adc0_default {
function = "ADC0";
groups = "ADC0";
};
pinctrl_adc1_default: adc1_default {
function = "ADC1";
groups = "ADC1";
};
pinctrl_adc10_default: adc10_default {
function = "ADC10";
groups = "ADC10";
};
pinctrl_adc11_default: adc11_default {
function = "ADC11";
groups = "ADC11";
};
pinctrl_adc12_default: adc12_default {
function = "ADC12";
groups = "ADC12";
};
pinctrl_adc13_default: adc13_default {
function = "ADC13";
groups = "ADC13";
};
pinctrl_adc14_default: adc14_default {
function = "ADC14";
groups = "ADC14";
};
pinctrl_adc15_default: adc15_default {
function = "ADC15";
groups = "ADC15";
};
pinctrl_adc2_default: adc2_default {
function = "ADC2";
groups = "ADC2";
};
pinctrl_adc3_default: adc3_default {
function = "ADC3";
groups = "ADC3";
};
pinctrl_adc4_default: adc4_default {
function = "ADC4";
groups = "ADC4";
};
pinctrl_adc5_default: adc5_default {
function = "ADC5";
groups = "ADC5";
};
pinctrl_adc6_default: adc6_default {
function = "ADC6";
groups = "ADC6";
};
pinctrl_adc7_default: adc7_default {
function = "ADC7";
groups = "ADC7";
};
pinctrl_adc8_default: adc8_default {
function = "ADC8";
groups = "ADC8";
};
pinctrl_adc9_default: adc9_default {
function = "ADC9";
groups = "ADC9";
};
pinctrl_bmcint_default: bmcint_default {
function = "BMCINT";
groups = "BMCINT";
};
pinctrl_ddcclk_default: ddcclk_default {
function = "DDCCLK";
groups = "DDCCLK";
};
pinctrl_ddcdat_default: ddcdat_default {
function = "DDCDAT";
groups = "DDCDAT";
};
pinctrl_espi_default: espi_default {
function = "ESPI";
groups = "ESPI";
};
pinctrl_fsi1_default: fsi1_default {
function = "FSI1";
groups = "FSI1";
};
pinctrl_fsi2_default: fsi2_default {
function = "FSI2";
groups = "FSI2";
};
pinctrl_fwspics1_default: fwspics1_default {
function = "FWSPICS1";
groups = "FWSPICS1";
};
pinctrl_fwspics2_default: fwspics2_default {
function = "FWSPICS2";
groups = "FWSPICS2";
};
pinctrl_gpid0_default: gpid0_default {
function = "GPID0";
groups = "GPID0";
};
pinctrl_gpid2_default: gpid2_default {
function = "GPID2";
groups = "GPID2";
};
pinctrl_gpid4_default: gpid4_default {
function = "GPID4";
groups = "GPID4";
};
pinctrl_gpid6_default: gpid6_default {
function = "GPID6";
groups = "GPID6";
};
pinctrl_gpie0_default: gpie0_default {
function = "GPIE0";
groups = "GPIE0";
};
pinctrl_gpie2_default: gpie2_default {
function = "GPIE2";
groups = "GPIE2";
};
pinctrl_gpie4_default: gpie4_default {
function = "GPIE4";
groups = "GPIE4";
};
pinctrl_gpie6_default: gpie6_default {
function = "GPIE6";
groups = "GPIE6";
};
pinctrl_i2c1_default: i2c1_default {
function = "I2C1";
groups = "I2C1";
};
ARM: dts: ast2600: Add I2C pinctrl Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 05:10:31 +00:00
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
pinctrl_i2c2_default: i2c2_default {
function = "I2C2";
groups = "I2C2";
};
pinctrl_i2c3_default: i2c3_default {
function = "I2C3";
groups = "I2C3";
};
pinctrl_i2c4_default: i2c4_default {
function = "I2C4";
groups = "I2C4";
};
pinctrl_i2c5_default: i2c5_default {
function = "I2C5";
groups = "I2C5";
};
pinctrl_i2c6_default: i2c6_default {
function = "I2C6";
groups = "I2C6";
};
pinctrl_i2c7_default: i2c7_default {
function = "I2C7";
groups = "I2C7";
};
pinctrl_i2c8_default: i2c8_default {
function = "I2C8";
groups = "I2C8";
};
pinctrl_i2c9_default: i2c9_default {
function = "I2C9";
groups = "I2C9";
};
pinctrl_i2c10_default: i2c10_default {
function = "I2C10";
groups = "I2C10";
};
pinctrl_i2c11_default: i2c11_default {
function = "I2C11";
groups = "I2C11";
};
pinctrl_i2c12_default: i2c12_default {
function = "I2C12";
groups = "I2C12";
};
pinctrl_i2c13_default: i2c13_default {
function = "I2C13";
groups = "I2C13";
};
pinctrl_i2c14_default: i2c14_default {
function = "I2C14";
groups = "I2C14";
};
pinctrl_i2c15_default: i2c15_default {
function = "I2C15";
groups = "I2C15";
};
pinctrl_i2c16_default: i2c16_default {
function = "I2C16";
groups = "I2C16";
};
pinctrl_lad0_default: lad0_default {
function = "LAD0";
groups = "LAD0";
};
pinctrl_lad1_default: lad1_default {
function = "LAD1";
groups = "LAD1";
};
pinctrl_lad2_default: lad2_default {
function = "LAD2";
groups = "LAD2";
};
pinctrl_lad3_default: lad3_default {
function = "LAD3";
groups = "LAD3";
};
pinctrl_lclk_default: lclk_default {
function = "LCLK";
groups = "LCLK";
};
pinctrl_lframe_default: lframe_default {
function = "LFRAME";
groups = "LFRAME";
};
pinctrl_lpchc_default: lpchc_default {
function = "LPCHC";
groups = "LPCHC";
};
pinctrl_lpcpd_default: lpcpd_default {
function = "LPCPD";
groups = "LPCPD";
};
pinctrl_lpcplus_default: lpcplus_default {
function = "LPCPLUS";
groups = "LPCPLUS";
};
pinctrl_lpcpme_default: lpcpme_default {
function = "LPCPME";
groups = "LPCPME";
};
pinctrl_lpcrst_default: lpcrst_default {
function = "LPCRST";
groups = "LPCRST";
};
pinctrl_lpcsmi_default: lpcsmi_default {
function = "LPCSMI";
groups = "LPCSMI";
};
pinctrl_lsirq_default: lsirq_default {
function = "LSIRQ";
groups = "LSIRQ";
};
pinctrl_mac1link_default: mac1link_default {
function = "MAC1LINK";
groups = "MAC1LINK";
};
pinctrl_mac2link_default: mac2link_default {
function = "MAC2LINK";
groups = "MAC2LINK";
};
pinctrl_mac3link_default: mac3link_default {
function = "MAC3LINK";
groups = "MAC3LINK";
};
pinctrl_mac4link_default: mac4link_default {
function = "MAC4LINK";
groups = "MAC4LINK";
};
pinctrl_mdio1_default: mdio1_default {
function = "MDIO1";
groups = "MDIO1";
};
pinctrl_mdio2_default: mdio2_default {
function = "MDIO2";
groups = "MDIO2";
};
pinctrl_mdio3_default: mdio3_default {
function = "MDIO3";
groups = "MDIO3";
};
pinctrl_mdio4_default: mdio4_default {
function = "MDIO4";
groups = "MDIO4";
};
pinctrl_rmii1_default: rmii1_default {
function = "RMII1";
groups = "RMII1";
};
pinctrl_rmii2_default: rmii2_default {
function = "RMII2";
groups = "RMII2";
};
pinctrl_rmii3_default: rmii3_default {
function = "RMII3";
groups = "RMII3";
};
pinctrl_rmii4_default: rmii4_default {
function = "RMII4";
groups = "RMII4";
};
pinctrl_rmii1rclk_default: rmii1rclk_default {
function = "RMII1RCLK";
groups = "RMII1RCLK";
};
pinctrl_rmii2rclk_default: rmii2rclk_default {
function = "RMII2RCLK";
groups = "RMII2RCLK";
};
pinctrl_rmii3rclk_default: rmii3rclk_default {
function = "RMII3RCLK";
groups = "RMII3RCLK";
};
pinctrl_rmii4rclk_default: rmii4rclk_default {
function = "RMII4RCLK";
groups = "RMII4RCLK";
};
pinctrl_ncts1_default: ncts1_default {
function = "NCTS1";
groups = "NCTS1";
};
pinctrl_ncts2_default: ncts2_default {
function = "NCTS2";
groups = "NCTS2";
};
pinctrl_ncts3_default: ncts3_default {
function = "NCTS3";
groups = "NCTS3";
};
pinctrl_ncts4_default: ncts4_default {
function = "NCTS4";
groups = "NCTS4";
};
pinctrl_ndcd1_default: ndcd1_default {
function = "NDCD1";
groups = "NDCD1";
};
pinctrl_ndcd2_default: ndcd2_default {
function = "NDCD2";
groups = "NDCD2";
};
pinctrl_ndcd3_default: ndcd3_default {
function = "NDCD3";
groups = "NDCD3";
};
pinctrl_ndcd4_default: ndcd4_default {
function = "NDCD4";
groups = "NDCD4";
};
pinctrl_ndsr1_default: ndsr1_default {
function = "NDSR1";
groups = "NDSR1";
};
pinctrl_ndsr2_default: ndsr2_default {
function = "NDSR2";
groups = "NDSR2";
};
pinctrl_ndsr3_default: ndsr3_default {
function = "NDSR3";
groups = "NDSR3";
};
pinctrl_ndsr4_default: ndsr4_default {
function = "NDSR4";
groups = "NDSR4";
};
pinctrl_ndtr1_default: ndtr1_default {
function = "NDTR1";
groups = "NDTR1";
};
pinctrl_ndtr2_default: ndtr2_default {
function = "NDTR2";
groups = "NDTR2";
};
pinctrl_ndtr3_default: ndtr3_default {
function = "NDTR3";
groups = "NDTR3";
};
pinctrl_ndtr4_default: ndtr4_default {
function = "NDTR4";
groups = "NDTR4";
};
pinctrl_nri1_default: nri1_default {
function = "NRI1";
groups = "NRI1";
};
pinctrl_nri2_default: nri2_default {
function = "NRI2";
groups = "NRI2";
};
pinctrl_nri3_default: nri3_default {
function = "NRI3";
groups = "NRI3";
};
pinctrl_nri4_default: nri4_default {
function = "NRI4";
groups = "NRI4";
};
pinctrl_nrts1_default: nrts1_default {
function = "NRTS1";
groups = "NRTS1";
};
pinctrl_nrts2_default: nrts2_default {
function = "NRTS2";
groups = "NRTS2";
};
pinctrl_nrts3_default: nrts3_default {
function = "NRTS3";
groups = "NRTS3";
};
pinctrl_nrts4_default: nrts4_default {
function = "NRTS4";
groups = "NRTS4";
};
pinctrl_oscclk_default: oscclk_default {
function = "OSCCLK";
groups = "OSCCLK";
};
pinctrl_pewake_default: pewake_default {
function = "PEWAKE";
groups = "PEWAKE";
};
pinctrl_pnor_default: pnor_default {
function = "PNOR";
groups = "PNOR";
};
pinctrl_pwm0_default: pwm0_default {
function = "PWM0";
groups = "PWM0";
};
pinctrl_pwm1_default: pwm1_default {
function = "PWM1";
groups = "PWM1";
};
pinctrl_pwm2_default: pwm2_default {
function = "PWM2";
groups = "PWM2";
};
pinctrl_pwm3_default: pwm3_default {
function = "PWM3";
groups = "PWM3";
};
pinctrl_pwm4_default: pwm4_default {
function = "PWM4";
groups = "PWM4";
};
pinctrl_pwm5_default: pwm5_default {
function = "PWM5";
groups = "PWM5";
};
pinctrl_pwm6_default: pwm6_default {
function = "PWM6";
groups = "PWM6";
};
pinctrl_pwm7_default: pwm7_default {
function = "PWM7";
groups = "PWM7";
};
pinctrl: Add the pinctrl setting for PWM. This patchs add the signal description array for PWM pinctrl settings. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-08 03:04:06 +00:00
pinctrl_pwm8g0_default: pwm8g0_default {
function = "PWM8G0";
groups = "PWM8G0";
};
pinctrl_pwm8g1_default: pwm8g1_default {
function = "PWM8G1";
groups = "PWM8G1";
};
pinctrl_pwm9g0_default: pwm9g0_default {
function = "PWM9G0";
groups = "PWM9G0";
};
pinctrl_pwm9g1_default: pwm9g1_default {
function = "PWM9G1";
groups = "PWM9G1";
};
pinctrl_pwm10g0_default: pwm10g0_default {
function = "PWM10G0";
groups = "PWM10G0";
};
pinctrl_pwm10g1_default: pwm10g1_default {
function = "PWM10G1";
groups = "PWM10G1";
};
pinctrl_pwm11g0_default: pwm11g0_default {
function = "PWM11G0";
groups = "PWM11G0";
};
pinctrl_pwm11g1_default: pwm11g1_default {
function = "PWM11G1";
groups = "PWM11G1";
};
pinctrl_pwm12g0_default: pwm12g0_default {
function = "PWM12G0";
groups = "PWM12G0";
};
pinctrl_pwm12g1_default: pwm12g1_default {
function = "PWM12G1";
groups = "PWM12G1";
};
pinctrl_pwm13g0_default: pwm13g0_default {
function = "PWM13G0";
groups = "PWM13G0";
};
pinctrl_pwm13g1_default: pwm13g1_default {
function = "PWM13G1";
groups = "PWM13G1";
};
pinctrl_pwm14g0_default: pwm14g0_default {
function = "PWM14G0";
groups = "PWM14G0";
};
pinctrl_pwm14g1_default: pwm14g1_default {
function = "PWM14G1";
groups = "PWM14G1";
};
pinctrl_pwm15g0_default: pwm15g0_default {
function = "PWM15G0";
groups = "PWM15G0";
};
pinctrl_pwm15g1_default: pwm15g1_default {
function = "PWM15G1";
groups = "PWM15G1";
};
ARM: dts: aspeed: Add AST2600 SoC support AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 05:54:27 +00:00
pinctrl_rgmii1_default: rgmii1_default {
function = "RGMII1";
groups = "RGMII1";
};
pinctrl_rgmii2_default: rgmii2_default {
function = "RGMII2";
groups = "RGMII2";
};
pinctrl_rgmii3_default: rgmii3_default {
function = "RGMII3";
groups = "RGMII3";
};
pinctrl_rgmii4_default: rgmii4_default {
function = "RGMII4";
groups = "RGMII4";
};
pinctrl_rmii1_default: rmii1_default {
function = "RMII1";
groups = "RMII1";
};
pinctrl_rmii2_default: rmii2_default {
function = "RMII2";
groups = "RMII2";
};
pinctrl_rxd1_default: rxd1_default {
function = "RXD1";
groups = "RXD1";
};
pinctrl_rxd2_default: rxd2_default {
function = "RXD2";
groups = "RXD2";
};
pinctrl_rxd3_default: rxd3_default {
function = "RXD3";
groups = "RXD3";
};
pinctrl_rxd4_default: rxd4_default {
function = "RXD4";
groups = "RXD4";
};
pinctrl_salt1_default: salt1_default {
function = "SALT1";
groups = "SALT1";
};
pinctrl_salt10_default: salt10_default {
function = "SALT10";
groups = "SALT10";
};
pinctrl_salt11_default: salt11_default {
function = "SALT11";
groups = "SALT11";
};
pinctrl_salt12_default: salt12_default {
function = "SALT12";
groups = "SALT12";
};
pinctrl_salt13_default: salt13_default {
function = "SALT13";
groups = "SALT13";
};
pinctrl_salt14_default: salt14_default {
function = "SALT14";
groups = "SALT14";
};
pinctrl_salt2_default: salt2_default {
function = "SALT2";
groups = "SALT2";
};
pinctrl_salt3_default: salt3_default {
function = "SALT3";
groups = "SALT3";
};
pinctrl_salt4_default: salt4_default {
function = "SALT4";
groups = "SALT4";
};
pinctrl_salt5_default: salt5_default {
function = "SALT5";
groups = "SALT5";
};
pinctrl_salt6_default: salt6_default {
function = "SALT6";
groups = "SALT6";
};
pinctrl_salt7_default: salt7_default {
function = "SALT7";
groups = "SALT7";
};
pinctrl_salt8_default: salt8_default {
function = "SALT8";
groups = "SALT8";
};
pinctrl_salt9_default: salt9_default {
function = "SALT9";
groups = "SALT9";
};
pinctrl_scl1_default: scl1_default {
function = "SCL1";
groups = "SCL1";
};
pinctrl_scl2_default: scl2_default {
function = "SCL2";
groups = "SCL2";
};
pinctrl_sd1_default: sd1_default {
function = "SD1";
groups = "SD1";
};
pinctrl_sd2_default: sd2_default {
function = "SD2";
groups = "SD2";
};
pinctrl_emmc_default: emmc_default {
function = "EMMC";
groups = "EMMC";
};
pinctrl_emmcg8_default: emmcg8_default {
function = "EMMCG8";
groups = "EMMCG8";
};
pinctrl_sda1_default: sda1_default {
function = "SDA1";
groups = "SDA1";
};
pinctrl_sda2_default: sda2_default {
function = "SDA2";
groups = "SDA2";
};
pinctrl_sgps1_default: sgps1_default {
function = "SGPS1";
groups = "SGPS1";
};
pinctrl_sgps2_default: sgps2_default {
function = "SGPS2";
groups = "SGPS2";
};
pinctrl_sioonctrl_default: sioonctrl_default {
function = "SIOONCTRL";
groups = "SIOONCTRL";
};
pinctrl_siopbi_default: siopbi_default {
function = "SIOPBI";
groups = "SIOPBI";
};
pinctrl_siopbo_default: siopbo_default {
function = "SIOPBO";
groups = "SIOPBO";
};
pinctrl_siopwreq_default: siopwreq_default {
function = "SIOPWREQ";
groups = "SIOPWREQ";
};
pinctrl_siopwrgd_default: siopwrgd_default {
function = "SIOPWRGD";
groups = "SIOPWRGD";
};
pinctrl_sios3_default: sios3_default {
function = "SIOS3";
groups = "SIOS3";
};
pinctrl_sios5_default: sios5_default {
function = "SIOS5";
groups = "SIOS5";
};
pinctrl_siosci_default: siosci_default {
function = "SIOSCI";
groups = "SIOSCI";
};
pinctrl_spi1_default: spi1_default {
function = "SPI1";
groups = "SPI1";
};
pinctrl_spi1cs1_default: spi1cs1_default {
function = "SPI1CS1";
groups = "SPI1CS1";
};
pinctrl_spi1debug_default: spi1debug_default {
function = "SPI1DEBUG";
groups = "SPI1DEBUG";
};
pinctrl_spi1passthru_default: spi1passthru_default {
function = "SPI1PASSTHRU";
groups = "SPI1PASSTHRU";
};
pinctrl_spi2ck_default: spi2ck_default {
function = "SPI2CK";
groups = "SPI2CK";
};
pinctrl_spi2cs0_default: spi2cs0_default {
function = "SPI2CS0";
groups = "SPI2CS0";
};
pinctrl_spi2cs1_default: spi2cs1_default {
function = "SPI2CS1";
groups = "SPI2CS1";
};
pinctrl_spi2miso_default: spi2miso_default {
function = "SPI2MISO";
groups = "SPI2MISO";
};
pinctrl_spi2mosi_default: spi2mosi_default {
function = "SPI2MOSI";
groups = "SPI2MOSI";
};
pinctrl_timer3_default: timer3_default {
function = "TIMER3";
groups = "TIMER3";
};
pinctrl_timer4_default: timer4_default {
function = "TIMER4";
groups = "TIMER4";
};
pinctrl_timer5_default: timer5_default {
function = "TIMER5";
groups = "TIMER5";
};
pinctrl_timer6_default: timer6_default {
function = "TIMER6";
groups = "TIMER6";
};
pinctrl_timer7_default: timer7_default {
function = "TIMER7";
groups = "TIMER7";
};
pinctrl_timer8_default: timer8_default {
function = "TIMER8";
groups = "TIMER8";
};
pinctrl_txd1_default: txd1_default {
function = "TXD1";
groups = "TXD1";
};
pinctrl_txd2_default: txd2_default {
function = "TXD2";
groups = "TXD2";
};
pinctrl_txd3_default: txd3_default {
function = "TXD3";
groups = "TXD3";
};
pinctrl_txd4_default: txd4_default {
function = "TXD4";
groups = "TXD4";
};
pinctrl_uart6_default: uart6_default {
function = "UART6";
groups = "UART6";
};
pinctrl_usbcki_default: usbcki_default {
function = "USBCKI";
groups = "USBCKI";
};
pinctrl_usb2ah_default: usb2ah_default {
function = "USB2AH";
groups = "USB2AH";
};
pinctrl_usb11bhid_default: usb11bhid_default {
function = "USB11BHID";
groups = "USB11BHID";
};
pinctrl_usb2bh_default: usb2bh_default {
function = "USB2BH";
groups = "USB2BH";
};
pinctrl_vgabiosrom_default: vgabiosrom_default {
function = "VGABIOSROM";
groups = "VGABIOSROM";
};
pinctrl_vgahs_default: vgahs_default {
function = "VGAHS";
groups = "VGAHS";
};
pinctrl_vgavs_default: vgavs_default {
function = "VGAVS";
groups = "VGAVS";
};
pinctrl_vpi24_default: vpi24_default {
function = "VPI24";
groups = "VPI24";
};
pinctrl_vpo_default: vpo_default {
function = "VPO";
groups = "VPO";
};
pinctrl_wdtrst1_default: wdtrst1_default {
function = "WDTRST1";
groups = "WDTRST1";
};
pinctrl_wdtrst2_default: wdtrst2_default {
function = "WDTRST2";
groups = "WDTRST2";
};
pinctrl_pcie0rc_default: pcie0rc_default {
function = "PCIE0RC";
groups = "PCIE0RC";
};
pinctrl_pcie1rc_default: pcie1rc_default {
function = "PCIE1RC";
groups = "PCIE1RC";
};
};
Reference in a new issue Copy permalink