2022-05-20 03:22:21 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef __CONFIG_MT7621_H
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#define __CONFIG_MT7621_H
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0x80000000
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2022-05-20 03:22:21 +00:00
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2022-12-04 15:04:50 +00:00
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#define CFG_MAX_MEM_MAPPED 0x1c000000
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2022-05-20 03:22:21 +00:00
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_SP_OFFSET 0x800000
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2022-05-20 03:22:21 +00:00
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/* MMC */
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#define MMC_SUPPORTS_TUNING
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/* NAND */
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/* Serial SPL */
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
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2022-11-16 18:10:28 +00:00
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#define CFG_SYS_NS16550_CLK 50000000
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#define CFG_SYS_NS16550_COM1 0xbe000c00
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2022-05-20 03:22:21 +00:00
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#endif
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/* Serial common */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
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2022-05-20 03:22:21 +00:00
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230400, 460800, 921600 }
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/* Dummy value */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_UBOOT_BASE 0
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2022-05-20 03:22:21 +00:00
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#endif /* __CONFIG_MT7621_H */
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