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270 lines
8.7 KiB
C
270 lines
8.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __BOARD_DDR_H__
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#define __BOARD_DDR_H__
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#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0 \
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{ {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} }
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#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES \
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0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08, \
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0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00, \
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0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00, \
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0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08, \
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0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b, \
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0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35, \
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0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35, \
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0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e, \
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0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18, \
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0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47, \
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0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31, \
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0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c, \
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0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39, \
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0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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#define OCTEON_NIC23_CFG0_SPD_VALUES NIC23_MTA8ATF51264AZ2G3_SPD_VALUES
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#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR 0x56
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#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
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.rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
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.dic_00 = ddr4_dic_34ohm, \
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.rtt_nom_00 = 0, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = 0, \
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.dic_01 = ddr4_dic_34ohm, \
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.rtt_nom_01 = 0, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.rtt_wr_10 = 0, \
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.dic_10 = ddr4_dic_34ohm, \
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.rtt_nom_10 = 0, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = 0, \
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.dic_11 = ddr4_dic_34ohm, \
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.rtt_nom_11 = 0, \
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} \
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}
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#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
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.rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
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.dic_00 = ddr4_dic_34ohm, \
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.rtt_nom_00 = 0, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = 0, \
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.dic_01 = ddr4_dic_34ohm, \
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.rtt_nom_01 = 0, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.rtt_wr_10 = ddr4_rttwr_80ohm & 3, \
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.rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
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.dic_10 = ddr4_dic_34ohm, \
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.rtt_nom_10 = 0, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = 0, \
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.dic_11 = ddr4_dic_34ohm, \
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.rtt_nom_11 = 0 \
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} \
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}
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#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_60ohm, \
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.vref_value_00 = 0x22, \
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.vref_range_00 = 0, \
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.rtt_park_01 = 0, \
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.vref_value_01 = 0, \
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.vref_range_01 = 0, \
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.rtt_park_10 = 0, \
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.vref_value_10 = 0, \
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.vref_range_10 = 0, \
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.rtt_park_11 = 0, \
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.vref_value_11 = 0, \
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.vref_range_11 = 0 \
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} \
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}
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#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_48ohm, \
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.vref_value_00 = 0x1f, \
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.vref_range_00 = 0, \
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.rtt_park_01 = 0, \
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.vref_value_01 = 0, \
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.vref_range_01 = 0, \
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.rtt_park_10 = ddr4_rttpark_48ohm, \
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.vref_value_10 = 0x1f, \
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.vref_range_10 = 0, \
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.rtt_park_11 = 0, \
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.vref_value_11 = 0, \
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.vref_range_11 = 0 \
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} \
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}
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#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
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/* 1 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x00000000ULL, \
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OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT, \
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OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT, \
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ddr4_rodt_ctl_48_ohm, \
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0x00000000ULL, \
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0 \
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}, \
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/* 2 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x00000000ULL, \
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OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT, \
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OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT, \
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ddr4_rodt_ctl_80_ohm, \
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0x00000000ULL, \
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0 \
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}
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/*
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* Construct a static initializer for the ddr_configuration_t variable that
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* holds (almost) all of the information required for DDR initialization.
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*/
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/*
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* The parameters below make up the custom_lmc_config data structure.
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* This structure is used to customize the way that the LMC DRAM
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* Controller is configured for a particular board design.
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*
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* Refer to the file lib_octeon_board_table_entry.h for a description
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* of the custom board settings. It is usually kept in the following
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* location... arch/mips/include/asm/arch-octeon/
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*
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*/
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#define OCTEON_NIC23_DDR_CONFIGURATION \
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/* Interface 0 */ \
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{ \
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.custom_lmc_config = { \
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.min_rtt_nom_idx = 2, \
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.max_rtt_nom_idx = 5, \
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.min_rodt_ctl = 2, \
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.max_rodt_ctl = 4, \
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.ck_ctl = ddr4_driver_34_ohm, \
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.cmd_ctl = ddr4_driver_34_ohm, \
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.ctl_ctl = ddr4_driver_34_ohm, \
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.min_cas_latency = 7, \
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.offset_en = 1, \
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.offset_udimm = 2, \
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.offset_rdimm = 2, \
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.ddr_rtt_nom_auto = 0, \
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.ddr_rodt_ctl_auto = 0, \
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.rlevel_compute = 0, \
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.ddr2t_udimm = 1, \
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.ddr2t_rdimm = 1, \
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.maximum_adjacent_rlevel_delay_increment = 2, \
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.fprch2 = 2, \
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.dll_write_offset = NULL, \
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.dll_read_offset = NULL, \
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.disable_sequential_delay_check = 1, \
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.parity = 0 \
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}, \
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.dimm_config_table = { \
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OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0, \
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DIMM_CONFIG_TERMINATOR \
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}, \
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.unbuffered = { \
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.ddr_board_delay = 0, \
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.lmc_delay_clk = 0, \
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.lmc_delay_cmd = 0, \
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.lmc_delay_dq = 0 \
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}, \
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.registered = { \
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.ddr_board_delay = 0, \
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.lmc_delay_clk = 0, \
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.lmc_delay_cmd = 0, \
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.lmc_delay_dq = 0 \
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}, \
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.odt_1rank_config = { \
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OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
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}, \
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},
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#endif /* __BOARD_DDR_H__ */
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