mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
120 lines
3 KiB
Text
120 lines
3 KiB
Text
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 PHYTEC Messtechnik
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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/ {
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display: display0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx-parallel-display";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_disp0>;
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interface-pix-fmt = "rgb24";
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status = "disabled";
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port@0 {
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reg = <0>;
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display0_in: endpoint {
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remote-endpoint = <&ipu1_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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display0_out: endpoint {
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remote-endpoint = <&peb_panel_lcd_in>;
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};
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};
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};
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panel-lcd {
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compatible = "edt,etm0700g0edh6";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_disp0_pwr>;
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power-supply = <®_display>;
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enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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backlight = <&backlight>;
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status = "disabled";
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port {
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peb_panel_lcd_in: endpoint {
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remote-endpoint = <&display0_out>;
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};
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};
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};
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reg_display: regulator-peb-display {
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compatible = "regulator-fixed";
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regulator-name = "peb-display";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&i2c1 {
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edt_ft5x06: touchscreen@38 {
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compatible = "edt,edt-ft5406";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_edt_ft5x06>;
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reg = <0x38>;
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interrupt-parent = <&gpio3>;
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interrupts = <2 IRQ_TYPE_NONE>;
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status = "disabled";
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};
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};
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&ipu1_di0_disp0 {
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remote-endpoint = <&display0_in>;
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};
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&iomuxc {
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pinctrl_disp0: disp0grp {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
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>;
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};
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pinctrl_disp0_pwr: disp0pwrgrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
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>;
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};
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pinctrl_edt_ft5x06: edtft5x06grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1
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>;
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};
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};
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