mirror of
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460 lines
11 KiB
C
460 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic DesignWare based PCIe host controller driver
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*
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* Copyright (c) 2021 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Based on pcie_dw_rockchip.c
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* Copyright (c) 2021 Rockchip, Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <pci.h>
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#include <power-domain.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <dm/device_compat.h>
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#include <linux/iopoll.h>
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#include <linux/delay.h>
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#include <linux/log2.h>
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#include <linux/bitfield.h>
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#include "pcie_dw_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct meson_pcie - Amlogic Meson DW PCIe controller state
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*
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* @pci: The common PCIe DW structure
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* @meson_cfg_base: The base address of vendor regs
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* @phy
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* @clk_port
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* @clk_general
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* @clk_pclk
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* @rsts
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* @rst_gpio: The #PERST signal for slot
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*/
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struct meson_pcie {
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/* Must be first member of the struct */
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struct pcie_dw dw;
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void *meson_cfg_base;
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struct phy phy;
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struct clk clk_port;
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struct clk clk_general;
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struct clk clk_pclk;
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struct reset_ctl_bulk rsts;
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struct gpio_desc rst_gpio;
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};
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#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
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#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
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#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
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/* PCIe specific config registers */
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#define PCIE_CFG0 0x0
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#define APP_LTSSM_ENABLE BIT(7)
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#define PCIE_CFG_STATUS12 0x30
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#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
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#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
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#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
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#define PCIE_CFG_STATUS17 0x44
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#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
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#define WAIT_LINKUP_TIMEOUT 4000
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#define PORT_CLK_RATE 100000000UL
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#define MAX_PAYLOAD_SIZE 256
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#define MAX_READ_REQ_SIZE 256
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#define PCIE_RESET_DELAY 500
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#define PCIE_SHARED_RESET 1
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#define PCIE_NORMAL_RESET 0
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enum pcie_data_rate {
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PCIE_GEN1,
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PCIE_GEN2,
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PCIE_GEN3,
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PCIE_GEN4
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};
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/* Parameters for the waiting for #perst signal */
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#define PERST_WAIT_US 1000000
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static inline u32 meson_cfg_readl(struct meson_pcie *priv, u32 reg)
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{
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return readl(priv->meson_cfg_base + reg);
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}
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static inline void meson_cfg_writel(struct meson_pcie *priv, u32 val, u32 reg)
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{
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writel(val, priv->meson_cfg_base + reg);
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}
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/**
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* meson_pcie_configure() - Configure link
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*
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* @meson_pcie: Pointer to the PCI controller state
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*
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* Configure the link mode and width
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*/
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static void meson_pcie_configure(struct meson_pcie *priv)
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{
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u32 val;
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dw_pcie_dbi_write_enable(&priv->dw, true);
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val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_FAST_LINK_MODE;
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val |= PORT_LINK_DLL_LINK_EN;
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val &= ~PORT_LINK_MODE_MASK;
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val |= PORT_LINK_MODE_1_LANES;
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writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
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val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
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val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
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writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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dw_pcie_dbi_write_enable(&priv->dw, false);
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}
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static inline void meson_pcie_enable_ltssm(struct meson_pcie *priv)
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{
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u32 val;
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val = meson_cfg_readl(priv, PCIE_CFG0);
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val |= APP_LTSSM_ENABLE;
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meson_cfg_writel(priv, val, PCIE_CFG0);
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}
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static int meson_pcie_wait_link_up(struct meson_pcie *priv)
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{
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u32 speed_okay = 0;
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u32 cnt = 0;
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u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
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do {
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state12 = meson_cfg_readl(priv, PCIE_CFG_STATUS12);
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state17 = meson_cfg_readl(priv, PCIE_CFG_STATUS17);
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smlh_up = IS_SMLH_LINK_UP(state12);
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rdlh_up = IS_RDLH_LINK_UP(state12);
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ltssm_up = IS_LTSSM_UP(state12);
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if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
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speed_okay = 1;
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if (smlh_up)
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debug("%s: smlh_link_up is on\n", __func__);
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if (rdlh_up)
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debug("%s: rdlh_link_up is on\n", __func__);
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if (ltssm_up)
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debug("%s: ltssm_up is on\n", __func__);
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if (speed_okay)
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debug("%s: speed_okay\n", __func__);
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if (smlh_up && rdlh_up && ltssm_up && speed_okay)
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return 0;
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cnt++;
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udelay(10);
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} while (cnt < WAIT_LINKUP_TIMEOUT);
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printf("%s: error: wait linkup timeout\n", __func__);
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return -EIO;
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}
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/**
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* meson_pcie_link_up() - Wait for the link to come up
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*
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* @meson_pcie: Pointer to the PCI controller state
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* @cap_speed: Desired link speed
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*
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* Return: 1 (true) for active line and negative (false) for no link (timeout)
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*/
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static int meson_pcie_link_up(struct meson_pcie *priv, u32 cap_speed)
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{
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/* DW link configurations */
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meson_pcie_configure(priv);
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/* Reset the device */
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if (dm_gpio_is_valid(&priv->rst_gpio)) {
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dm_gpio_set_value(&priv->rst_gpio, 1);
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/*
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* Minimal is 100ms from spec but we see
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* some wired devices need much more, such as 600ms.
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* Add a enough delay to cover all cases.
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*/
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udelay(PERST_WAIT_US);
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dm_gpio_set_value(&priv->rst_gpio, 0);
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}
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/* Enable LTSSM */
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meson_pcie_enable_ltssm(priv);
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return meson_pcie_wait_link_up(priv);
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}
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static int meson_size_to_payload(int size)
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{
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/*
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* dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
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* So if input size is not 2^order alignment or less than 2^7 or bigger
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* than 2^12, just set to default size 2^(1+7).
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*/
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if (!is_power_of_2(size) || size < 128 || size > 4096) {
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debug("%s: payload size %d, set to default 256\n", __func__, size);
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return 1;
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}
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return fls(size) - 8;
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}
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static void meson_set_max_payload(struct meson_pcie *priv, int size)
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{
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u32 val;
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u16 offset = dm_pci_find_capability(priv->dw.dev, PCI_CAP_ID_EXP);
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int max_payload_size = meson_size_to_payload(size);
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dw_pcie_dbi_write_enable(&priv->dw, true);
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL);
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val &= ~PCI_EXP_DEVCTL_PAYLOAD;
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writel(val, priv->dw.dbi_base + offset + PCI_EXP_DEVCTL);
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL);
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val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
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writel(val, priv->dw.dbi_base + PCI_EXP_DEVCTL);
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dw_pcie_dbi_write_enable(&priv->dw, false);
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}
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static void meson_set_max_rd_req_size(struct meson_pcie *priv, int size)
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{
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u32 val;
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u16 offset = dm_pci_find_capability(priv->dw.dev, PCI_CAP_ID_EXP);
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int max_rd_req_size = meson_size_to_payload(size);
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dw_pcie_dbi_write_enable(&priv->dw, true);
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL);
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val &= ~PCI_EXP_DEVCTL_PAYLOAD;
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writel(val, priv->dw.dbi_base + offset + PCI_EXP_DEVCTL);
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL);
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val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
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writel(val, priv->dw.dbi_base + PCI_EXP_DEVCTL);
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dw_pcie_dbi_write_enable(&priv->dw, false);
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}
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static int meson_pcie_init_port(struct udevice *dev)
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{
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int ret;
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struct meson_pcie *priv = dev_get_priv(dev);
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ret = generic_phy_init(&priv->phy);
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if (ret) {
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dev_err(dev, "failed to init phy (ret=%d)\n", ret);
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return ret;
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}
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ret = generic_phy_power_on(&priv->phy);
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if (ret) {
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dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
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goto err_exit_phy;
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}
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ret = generic_phy_reset(&priv->phy);
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if (ret) {
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dev_err(dev, "failed to reset phy (ret=%d)\n", ret);
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goto err_exit_phy;
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}
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ret = reset_assert_bulk(&priv->rsts);
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if (ret) {
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dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
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goto err_power_off_phy;
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}
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udelay(PCIE_RESET_DELAY);
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ret = reset_deassert_bulk(&priv->rsts);
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if (ret) {
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dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);
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goto err_power_off_phy;
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}
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udelay(PCIE_RESET_DELAY);
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ret = clk_set_rate(&priv->clk_port, PORT_CLK_RATE);
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if (ret) {
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dev_err(dev, "failed to set port clk rate (ret=%d)\n", ret);
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goto err_deassert_bulk;
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}
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ret = clk_enable(&priv->clk_general);
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if (ret) {
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dev_err(dev, "failed to enable clk general (ret=%d)\n", ret);
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goto err_deassert_bulk;
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}
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ret = clk_enable(&priv->clk_pclk);
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if (ret) {
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dev_err(dev, "failed to enable pclk (ret=%d)\n", ret);
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goto err_deassert_bulk;
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}
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meson_set_max_payload(priv, MAX_PAYLOAD_SIZE);
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meson_set_max_rd_req_size(priv, MAX_READ_REQ_SIZE);
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pcie_dw_setup_host(&priv->dw);
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ret = meson_pcie_link_up(priv, LINK_SPEED_GEN_2);
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if (ret < 0)
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goto err_link_up;
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return 0;
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err_link_up:
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clk_disable(&priv->clk_port);
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clk_disable(&priv->clk_general);
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clk_disable(&priv->clk_pclk);
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err_deassert_bulk:
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reset_assert_bulk(&priv->rsts);
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err_power_off_phy:
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generic_phy_power_off(&priv->phy);
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err_exit_phy:
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generic_phy_exit(&priv->phy);
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return ret;
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}
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static int meson_pcie_parse_dt(struct udevice *dev)
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{
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struct meson_pcie *priv = dev_get_priv(dev);
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int ret;
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priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
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if (!priv->dw.dbi_base)
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return -ENODEV;
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dev_dbg(dev, "ELBI address is 0x%p\n", priv->dw.dbi_base);
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priv->meson_cfg_base = (void *)dev_read_addr_index(dev, 1);
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if (!priv->meson_cfg_base)
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return -ENODEV;
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dev_dbg(dev, "CFG address is 0x%p\n", priv->meson_cfg_base);
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ret = gpio_request_by_name(dev, "reset-gpios", 0,
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&priv->rst_gpio, GPIOD_IS_OUT);
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if (ret) {
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dev_err(dev, "failed to find reset-gpios property\n");
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return ret;
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}
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ret = reset_get_bulk(dev, &priv->rsts);
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if (ret) {
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dev_err(dev, "Can't get reset: %d\n", ret);
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return ret;
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}
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ret = clk_get_by_name(dev, "port", &priv->clk_port);
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if (ret) {
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dev_err(dev, "Can't get port clock: %d\n", ret);
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return ret;
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}
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ret = clk_get_by_name(dev, "general", &priv->clk_general);
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if (ret) {
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dev_err(dev, "Can't get port clock: %d\n", ret);
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return ret;
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}
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ret = clk_get_by_name(dev, "pclk", &priv->clk_pclk);
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if (ret) {
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dev_err(dev, "Can't get port clock: %d\n", ret);
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return ret;
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}
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ret = generic_phy_get_by_index(dev, 0, &priv->phy);
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if (ret) {
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dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
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return ret;
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}
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return 0;
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}
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/**
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* meson_pcie_probe() - Probe the PCIe bus for active link
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*
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* @dev: A pointer to the device being operated on
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*
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* Probe for an active link on the PCIe bus and configure the controller
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* to enable this port.
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*
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* Return: 0 on success, else -ENODEV
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*/
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static int meson_pcie_probe(struct udevice *dev)
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{
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struct meson_pcie *priv = dev_get_priv(dev);
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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int ret = 0;
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priv->dw.first_busno = dev_seq(dev);
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priv->dw.dev = dev;
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||
|
|
||
|
ret = meson_pcie_parse_dt(dev);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
ret = meson_pcie_init_port(dev);
|
||
|
if (ret) {
|
||
|
dm_gpio_free(dev, &priv->rst_gpio);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
|
||
|
dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
|
||
|
pcie_dw_get_link_width(&priv->dw),
|
||
|
hose->first_busno);
|
||
|
|
||
|
return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
|
||
|
PCIE_ATU_REGION_INDEX0,
|
||
|
PCIE_ATU_TYPE_MEM,
|
||
|
priv->dw.mem.phys_start,
|
||
|
priv->dw.mem.bus_start,
|
||
|
priv->dw.mem.size);
|
||
|
}
|
||
|
|
||
|
static const struct dm_pci_ops meson_pcie_ops = {
|
||
|
.read_config = pcie_dw_read_config,
|
||
|
.write_config = pcie_dw_write_config,
|
||
|
};
|
||
|
|
||
|
static const struct udevice_id meson_pcie_ids[] = {
|
||
|
{ .compatible = "amlogic,axg-pcie" },
|
||
|
{ .compatible = "amlogic,g12a-pcie" },
|
||
|
{ }
|
||
|
};
|
||
|
|
||
|
U_BOOT_DRIVER(meson_dw_pcie) = {
|
||
|
.name = "pcie_dw_meson",
|
||
|
.id = UCLASS_PCI,
|
||
|
.of_match = meson_pcie_ids,
|
||
|
.ops = &meson_pcie_ops,
|
||
|
.probe = meson_pcie_probe,
|
||
|
.priv_auto = sizeof(struct meson_pcie),
|
||
|
};
|