2011-11-26 19:04:49 +00:00
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/*
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* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-11-26 19:04:49 +00:00
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*/
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#ifndef __ASM_OPENRISC_CACHE_H_
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#define __ASM_OPENRISC_CACHE_H_
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/*
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* Valid L1 data cache line sizes for the OpenRISC architecture are
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* 16 and 32 bytes.
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* If the board configuration has not specified one we default to the
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* largest of these values for alignment of DMA buffers.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 32
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#endif
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#endif /* __ASM_OPENRISC_CACHE_H_ */
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