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30 lines
825 B
C
30 lines
825 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
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*/
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#ifndef __CONFIG_ZYNQMP_R5_H
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#define __CONFIG_ZYNQMP_R5_H
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#define CONFIG_EXTRA_ENV_SETTINGS
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/* Serial drivers */
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/* Boot configuration */
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* Extend size of kernel image for uncompression */
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#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
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#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
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