mirror of
https://github.com/AsahiLinux/u-boot
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91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2021 Collabora Ltd.
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*/
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#ifndef __IMX8MN_VAR_SOM_H
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#define __IMX8MN_VAR_SOM_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
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#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#define CONFIG_SPL_STACK 0x980000
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#define CONFIG_SPL_BSS_START_ADDR 0x950000
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 2) \
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func(MMC, mmc, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na) \
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#include <config_distro_bootcmd.h>
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/* ENET */
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#if defined(CONFIG_FEC_MXC)
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_XCV_TYPE RGMII
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#endif /* CONFIG_FEC_MXC */
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"ramdisk_addr_r=0x43800000\0" \
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"fdt_addr_r=0x43000000\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"fastboot_partition_alias_all=" \
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__stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \
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"fastboot_partition_alias_bootloader=" \
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__stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \
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"emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \
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"emmc_ack=1\0" \
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"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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MEM_LAYOUT_ENV_SETTINGS \
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BOOTENV
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
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#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* USDHC */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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/* I2C */
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#define CONFIG_SYS_I2C_SPEED 400000
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#endif /* __IMX8MN_VAR_SOM_H */
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