2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2016-06-05 00:43:00 +00:00
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/*
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* (C) Copyright 2015, Freescale Semiconductor, Inc.
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*/
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#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
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#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
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#define MC_RGM_DES (MC_RGM_BASE_ADDR)
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#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
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#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
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#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
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#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
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#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
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#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
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#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
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#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
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#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
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#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
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/* function reset sources mask */
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#define F_SWT4 0x8000
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#define F_JTAG 0x400
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#define F_FCCU_SOFT 0x40
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#define F_FCCU_HARD 0x20
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#define F_SOFT_FUNC 0x8
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#define F_ST_DONE 0x4
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#define F_EXT_RST 0x1
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#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */
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