2018-11-02 14:21:05 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: Common Architecture initialization
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <spl.h>
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#include "common.h"
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#include <dm.h>
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#include <remoteproc.h>
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2019-03-08 06:17:33 +00:00
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#include <linux/soc/ti/ti_sci_protocol.h>
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2019-03-08 06:17:34 +00:00
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#include <fdt_support.h>
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2019-06-07 13:54:42 +00:00
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#include <asm/arch/sys_proto.h>
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2019-03-08 06:17:33 +00:00
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struct ti_sci_handle *get_ti_sci_handle(void)
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{
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struct udevice *dev;
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int ret;
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2019-09-09 07:17:37 +00:00
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ret = uclass_get_device(UCLASS_FIRMWARE, 0, &dev);
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2019-03-08 06:17:33 +00:00
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if (ret)
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panic("Failed to get SYSFW (%d)\n", ret);
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return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
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}
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2018-11-02 14:21:05 +00:00
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#ifdef CONFIG_SYS_K3_SPL_ATF
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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2019-06-07 13:54:43 +00:00
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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2018-11-02 14:21:05 +00:00
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int ret;
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2019-06-07 13:54:43 +00:00
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/* Release all the exclusive devices held by SPL before starting ATF */
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ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
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2018-11-02 14:21:05 +00:00
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/*
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* It is assumed that remoteproc device 1 is the corresponding
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2019-02-04 18:58:47 +00:00
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* Cortex-A core which runs ATF. Make sure DT reflects the same.
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2018-11-02 14:21:05 +00:00
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*/
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ret = rproc_dev_init(1);
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2019-02-04 18:58:47 +00:00
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if (ret)
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panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
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ret);
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2018-11-02 14:21:05 +00:00
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ret = rproc_load(1, spl_image->entry_point, 0x200);
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2019-02-04 18:58:47 +00:00
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if (ret)
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panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
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2018-11-02 14:21:05 +00:00
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2019-02-04 18:58:47 +00:00
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/* Add an extra newline to differentiate the ATF logs from SPL */
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2018-11-02 14:21:05 +00:00
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printf("Starting ATF on ARM64 core...\n\n");
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ret = rproc_start(1);
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2019-02-04 18:58:47 +00:00
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if (ret)
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panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
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2018-11-02 14:21:05 +00:00
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2019-06-07 13:54:42 +00:00
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debug("Releasing resources...\n");
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release_resources_for_core_shutdown();
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debug("Finalizing core shutdown...\n");
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2018-11-02 14:21:05 +00:00
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while (1)
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asm volatile("wfe");
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}
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#endif
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2019-03-08 06:17:34 +00:00
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#if defined(CONFIG_OF_LIBFDT)
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int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
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{
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u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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int ret, node, subnode, len, prev_node;
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u32 range[4], addr, size;
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const fdt32_t *sub_reg;
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ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
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msmc_size = msmc_end - msmc_start + 1;
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debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
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msmc_start, msmc_size);
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/* find or create "msmc_sram node */
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ret = fdt_path_offset(blob, parent_path);
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if (ret < 0)
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return ret;
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node = fdt_find_or_add_subnode(blob, ret, node_name);
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if (node < 0)
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return node;
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ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
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if (ret < 0)
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return ret;
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reg[0] = cpu_to_fdt64(msmc_start);
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reg[1] = cpu_to_fdt64(msmc_size);
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ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
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if (ret < 0)
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return ret;
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fdt_setprop_cell(blob, node, "#address-cells", 1);
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fdt_setprop_cell(blob, node, "#size-cells", 1);
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range[0] = 0;
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range[1] = cpu_to_fdt32(msmc_start >> 32);
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range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
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range[3] = cpu_to_fdt32(msmc_size);
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ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
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if (ret < 0)
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return ret;
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subnode = fdt_first_subnode(blob, node);
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prev_node = 0;
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/* Look for invalid subnodes and delete them */
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while (subnode >= 0) {
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sub_reg = fdt_getprop(blob, subnode, "reg", &len);
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addr = fdt_read_number(sub_reg, 1);
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sub_reg++;
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size = fdt_read_number(sub_reg, 1);
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debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
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subnode, addr, size);
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if (addr + size > msmc_size ||
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!strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
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!strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
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fdt_del_node(blob, subnode);
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debug("%s: deleting subnode %d\n", __func__, subnode);
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if (!prev_node)
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subnode = fdt_first_subnode(blob, node);
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else
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subnode = fdt_next_subnode(blob, prev_node);
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} else {
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prev_node = subnode;
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subnode = fdt_next_subnode(blob, prev_node);
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}
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}
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return 0;
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}
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2019-09-17 21:15:40 +00:00
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int fdt_disable_node(void *blob, char *node_path)
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{
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int offs;
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int ret;
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offs = fdt_path_offset(blob, node_path);
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if (offs < 0) {
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debug("Node %s not found.\n", node_path);
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return 0;
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}
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ret = fdt_setprop_string(blob, offs, "status", "disabled");
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if (ret < 0) {
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printf("Could not add status property to node %s: %s\n",
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node_path, fdt_strerror(ret));
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return ret;
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}
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return 0;
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}
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2019-03-08 06:17:34 +00:00
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#endif
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arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
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#ifndef CONFIG_SYSRESET
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void reset_cpu(ulong ignored)
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{
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}
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#endif
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