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u-boot/arch/arm/mach-versal/Kconfig

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arm64: versal: Add support for new Xilinx Versal ACAPs Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-22 12:55:27 +00:00
# SPDX-License-Identifier: GPL-2.0+
if ARCH_VERSAL
config SYS_BOARD
string "Board name"
default "versal"
config SYS_VENDOR
string "Vendor name"
default "xilinx"
config SYS_SOC
default "versal"
config SYS_CONFIG_NAME
string "Board configuration name"
default "xilinx_versal"
help
This option contains information about board configuration name.
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
config GICV3
def_bool y
config SYS_MALLOC_LEN
default 0x2000000
config COUNTER_FREQUENCY
int "Timer clock frequency"
default 0
help
Setup time clock frequency for certain platform
config ZYNQ_SDHCI_MAX_FREQ
default 200000000
arm64: versal: Move IOU_SWITCH_DIVISOR0 to Kconfig Move hardcoded IOU_SWITCH_DIVISOR0 to Kconfig to be able to set it up for different platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-28 10:12:41 +00:00
config IOU_SWITCH_DIVISOR0
hex "IOU switch divisor0"
default 0x20
help
Setup time clock divisor for input clock.
arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU This patch adds new config option which is used for reserving a specific memory for MMU Table and in this case we are using TCM for that purpose. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-08 16:17:26 +00:00
config SYS_MEM_RSVD_FOR_MMU
bool "Reserve memory for MMU Table"
help
If defined this option is used to setup different space for
MMU table than the one which will be allocated during
relocation.
arm64: zynqmp: Provide a Kconfig option to disable OCM and TCM MMU mapping This patch provides an option to enable/disable OCM and TCM memory into MMU table with corresponding memory attributes. The same change was done for ZynqMP by commit 189bec47ab1f ("arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-09-11 07:39:59 +00:00
config DEFINE_TCM_OCM_MMAP
bool "Define TCM and OCM memory in MMU Table"
default y if MP
help
This option if enabled defines the TCM and OCM memory and its
memory attributes in MMU table entry.
arm64: versal: Disable DDR cache mapping if DDR is not enabled Similar change was done in past by commit 3b644a3c2f69 ("arm64: zynqmp: Provide a config to not map DDR region in MMU table"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-03-18 12:45:21 +00:00
config VERSAL_NO_DDR
bool "Disable DDR MMU mapping"
help
This option configures MMU with no DDR to avoid speculative
access to DDR memory where DDR is not present.
arm64: versal: Add support for new Xilinx Versal ACAPs Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-22 12:55:27 +00:00
endif
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