mirror of
https://github.com/AsahiLinux/u-boot
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58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* Based on code from coreboot src/soc/intel/broadwell/me_status.c
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/arch/me.h>
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static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset)
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{
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u32 dword;
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dm_pci_read_config32(dev, offset, &dword);
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memcpy(ptr, &dword, sizeof(dword));
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}
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int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
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uint16_t *checksump)
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{
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int count;
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u32 hsiover;
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struct me_hfs hfs;
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/* Query for HSIO version, overloads H_GS and HFS */
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dm_pci_write_config32(dev, PCI_ME_H_GS,
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ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
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/* Must wait for ME acknowledgement */
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for (count = ME_RETRY; count > 0; --count) {
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me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
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if (hfs.bios_msg_ack)
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break;
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udelay(ME_DELAY);
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}
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if (!count) {
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debug("ERROR: ME failed to respond\n");
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return -ETIMEDOUT;
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}
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/* HSIO version should be in HFS_5 */
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dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
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*versionp = hsiover >> 16;
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*checksump = hsiover & 0xffff;
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debug("ME: HSIO Version : %d (CRC 0x%04x)\n",
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*versionp, *checksump);
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/* Reset registers to normal behavior */
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dm_pci_write_config32(dev, PCI_ME_H_GS,
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ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
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return 0;
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}
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