2006-02-21 23:43:16 +00:00
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/*
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* Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
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*/
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#define SDRAM_DDR 0 /* is SDR */
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/* Settings for XLB = 132 MHz */
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2006-03-06 22:18:48 +00:00
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#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
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#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
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#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
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#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
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