2012-12-03 13:56:51 +00:00
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/dts-v1/;
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2013-07-24 17:09:20 +00:00
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/include/ "coreboot.dtsi"
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2012-12-03 13:56:51 +00:00
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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config {
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silent_console = <0>;
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};
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gpio: gpio {};
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serial {
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reg = <0x3f8 8>;
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clock-frequency = <115200>;
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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2013-03-11 06:08:10 +00:00
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9";
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spi-flash@0 {
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reg = <0>;
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compatible = "winbond,w25q64", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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};
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};
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2012-12-03 13:56:51 +00:00
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};
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