2022-07-12 07:12:11 +00:00
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm QCS404
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(31)
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2023-02-01 13:58:50 +00:00
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#define CFG_CLK_SRC_GPLL1 BIT(8)
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#define GPLL1_STATUS_ACTIVE BIT(31)
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2022-07-12 07:12:11 +00:00
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static struct vote_clk gcc_blsp1_ahb_clk = {
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.cbcr_reg = BLSP1_AHB_CBCR,
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.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
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.vote_bit = BIT(10) | BIT(5) | BIT(4),
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};
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static const struct bcr_regs uart2_regs = {
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.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
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.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
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.M = BLSP1_UART2_APPS_M,
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.N = BLSP1_UART2_APPS_N,
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.D = BLSP1_UART2_APPS_D,
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};
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static const struct bcr_regs sdc_regs = {
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.cfg_rcgr = SDCC_CFG_RCGR(1),
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.cmd_rcgr = SDCC_CMD_RCGR(1),
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.M = SDCC_M(1),
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.N = SDCC_N(1),
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.D = SDCC_D(1),
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};
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static struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = BIT(0),
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};
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2023-02-01 13:58:50 +00:00
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static struct pll_vote_clk gpll1_vote_clk = {
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.status = GPLL1_STATUS,
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.status_bit = GPLL1_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = BIT(1),
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};
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2022-08-04 14:27:15 +00:00
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static const struct bcr_regs usb30_master_regs = {
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.cfg_rcgr = USB30_MASTER_CFG_RCGR,
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.cmd_rcgr = USB30_MASTER_CMD_RCGR,
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.M = USB30_MASTER_M,
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.N = USB30_MASTER_N,
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.D = USB30_MASTER_D,
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};
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2023-02-01 13:58:50 +00:00
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static const struct bcr_regs emac_regs = {
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.cfg_rcgr = EMAC_CFG_RCGR,
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.cmd_rcgr = EMAC_CMD_RCGR,
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.M = EMAC_M,
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.N = EMAC_N,
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.D = EMAC_D,
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};
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static const struct bcr_regs emac_ptp_regs = {
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.cfg_rcgr = EMAC_PTP_CFG_RCGR,
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.cmd_rcgr = EMAC_PTP_CMD_RCGR,
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.M = EMAC_M,
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.N = EMAC_N,
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.D = EMAC_D,
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};
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2022-07-12 07:12:11 +00:00
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ulong msm_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_BLSP1_UART2_APPS_CLK:
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/* UART: 115200 */
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clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
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CFG_CLK_SRC_CXO);
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clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
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break;
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case GCC_BLSP1_AHB_CLK:
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clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
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break;
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case GCC_SDCC1_APPS_CLK:
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/* SDCC1: 200MHz */
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clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
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CFG_CLK_SRC_GPLL0);
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
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break;
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case GCC_SDCC1_AHB_CLK:
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clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
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break;
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2023-02-01 13:58:50 +00:00
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case GCC_ETH_RGMII_CLK:
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if (rate == 250000000)
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clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
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CFG_CLK_SRC_GPLL1);
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else if (rate == 125000000)
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clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
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CFG_CLK_SRC_GPLL1);
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else if (rate == 50000000)
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clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
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CFG_CLK_SRC_GPLL1);
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else if (rate == 5000000)
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clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
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CFG_CLK_SRC_GPLL1);
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break;
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2022-07-12 07:12:11 +00:00
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default:
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return 0;
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}
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return 0;
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}
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2022-08-04 14:27:14 +00:00
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int msm_enable(struct clk *clk)
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{
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2022-08-04 14:27:15 +00:00
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_USB30_MASTER_CLK:
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clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
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clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
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CFG_CLK_SRC_GPLL0);
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break;
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case GCC_SYS_NOC_USB3_CLK:
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clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
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break;
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case GCC_USB30_SLEEP_CLK:
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clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
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break;
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case GCC_USB30_MOCK_UTMI_CLK:
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clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
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break;
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case GCC_USB_HS_PHY_CFG_AHB_CLK:
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clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
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break;
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case GCC_USB2A_PHY_SLEEP_CLK:
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clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
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break;
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2023-02-01 13:58:50 +00:00
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case GCC_ETH_PTP_CLK:
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/* SPEED_1000: freq -> 250MHz */
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clk_enable_cbc(priv->base + ETH_PTP_CBCR);
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clk_enable_gpll0(priv->base, &gpll1_vote_clk);
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clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
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CFG_CLK_SRC_GPLL1);
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break;
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case GCC_ETH_RGMII_CLK:
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/* SPEED_1000: freq -> 250MHz */
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clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
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clk_enable_gpll0(priv->base, &gpll1_vote_clk);
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clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
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CFG_CLK_SRC_GPLL1);
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break;
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case GCC_ETH_SLAVE_AHB_CLK:
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clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
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break;
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case GCC_ETH_AXI_CLK:
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clk_enable_cbc(priv->base + ETH_AXI_CBCR);
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break;
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2022-08-04 14:27:15 +00:00
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default:
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return 0;
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}
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2022-08-04 14:27:14 +00:00
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return 0;
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}
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